They have gone into the basic details though. When the...

They have gone into the basic details though.

When the development program commenced at IMEC, the initial lots were non platform lots, they explained they were about developing a method to fabricate individual memory cells and work out the window of process conditions they successfully fabricated in.

Once they had the process window worked out, they then went into Platform Lots, starting with just the Megabit memory array in PL1 first, then building the control layer on top in subsequent lots. I can't remember exactly when but full PCMO was achieved in an interim lot which changed everything.

PL2 was a partial failure which led to a delay in PL3 as an etch was developed. PL3 failed despite the etch. PL4 came along and it worked! That was supposed to be enough but now the company is trying to take it to 20nm.