https://www.i-micronews.com/a-guided-tour-across-the-nvm-technolo...

https://www.i-micronews.com/a-guided-tour-across-the-nvm-technology-landscape-an-interview-with-imec/?cn-reloaded=1

Memory program director at IMEC saying universal memory does not exist....planted cover story if ever Ive seen one

Also Orders of Magnitude rings a bell,,,where have I seen that before.....

I would like to stress that foundries or IDMs are not willing to adopt a new technology if that does not show a real potential for disruption. It is not enough to demonstrate a factor of 2-3 better performance or smaller cell size compared to existing technologies. The improvement should be measured in orders of magnitude!


What is the typical time required for developing from lab prototypes to functional Mb-class arrays? What are the key requirements to demonstrate the viability of a technology for commercial production?

I can give you a very good example related to resistive RAM technologies. It takes almost seven-to-eight years, from a laboratory device (proof-of-concept) to a large megabit array.

Where do you expect major technology breakthrough coming from in the coming years? From new materials and/or new device architectures?

I think the breakthrough needs to come from the memory-switching mechanism, which has not evolved significantly over the last decades.

And to be honest I dont even know if we are on step 2 or 3...
For developing a new memory technology, we typically start from the single-cell device level and we study the performance, the reliability, and several other figures of merit. Once we see that the technology has strong potential, then we move to a megabit-array layout to acquire more confidence through large-data statistics, and after validation we start making full megabit arrays. To that purpose, the test chip with the full megabit arrays. The wafer with the FEOL (including logic circuitry) is then taped out by our foundry partner and we integrate the BEOL with all the memory elements.