Probably late to make a comment.
while I agree this could be handled better and comms made differently on the approach. This is what I refer to as bleeding (leading) edge tech, there is constantly going to be stuff you don’t see coming. I think they have realised this could be loads more valuable if the testing was across the entire cell rather than a limited portion as per standard, possibly significantly increasing capabilities, something that is only just coming to light.
im not sure why everyone things PL5 was a failure, they always planned to do two together with one informing the other, my understanding was that was the intention all along, this paragraph in the announcement then supports that.
“The main purpose of the Fifth Platform Lot was to optimize the memory stack, specifically to accommodatescalability to 20nm size memory cell array incorporated in the Sixth Platform Lot. Using the proven cell size of60nm array (demonstrated i
n the Fourth Platform Lot), the Fifth Platform Lot seeks to uncover any processingadversity that could arise when scaling the memory cell stack necessary for successful construction of 20nm cellarray in the Sixth Platform Lot. Both Fifth and Sixth Platform Lots are fabricated with similar scaled memory stacks.”
while I seriously hate hearing DM say again that it’s another pivotal year for the company, another instance of this is what we hoped for and getting what is likely to be a 15month to 2yr delay.
I actually see this as a good outcome.
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Probably late to make a comment.while I agree this could be...
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