I agree with you.
We have been told that there is a trade off between retention and endurance at the same speed for our memory cells.
To increase retention, the cell can be written with a higher voltage or for a longer pulse duration, but this reduces endurance- there is a trade off.
The current required to write to a 20nm cell is 9x smaller than the 60nm cell, because our power consumption reduces with cell size- being a non filamentary technology.
But what happens if the Dory platform itself cannot function if power is cut 9x? (I.e if the transistors cease working properly with this type of power drop? Entirely feasible as 4DS are the first memory fabricated on 20nm Dory and Imec have not dealt with non filamentary memory at the bleeding edge before- only "me too" filamentary technology.)
Then 4ds can prove 20nm lot works with 9x the power, but there will be a loss of endurance and its upper limit cannot be characterised. Similarly the lower limit of retention too cannot be characterised. This is only because Dory can't operate with 9x less power.
Hence the need for a new platform designed by Infineon that can run on 9x less power. Come in spinner.
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I agree with you.We have been told that there is a trade off...
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