That is not correct. 4DS has developed a megabit array and gone to 60nm connected to the IMEC standard memory controller at 60nm which worked successfully in PL4. The "test kit" as you describe it is irrelevant. It does not aid the thing working. It is how you test whether it worked and what the performance is.
Individual cells were taken down to 40nm pre IMEC and not in a megabit array and they also worked. This was during the phase where the cells were being developed. As they were not in a megabit array, they did not use a memory controller.
At the time of PL3 & PL4, IMEC was not capable of going below 60nm for the megabit memory array & controller so that was the scale chosen for PL3 & PL4 first run of the megabit array. After PL4 IMEC added the 20nm equipment so they were then able to offer scaling down to 20nm, which 4DS decided to accept for PL6.
From where are you getting this odd set of facts and interpretations?
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