You keep repeating this line about PL5 being a failure, but I think you are not fully understanding what the issues are here. Broadly there are two components involved in the platform lots being built: 1.l The memory cell array - that bit is the 4DS tech, and 2. The memory controller - that bit is IMEC tech and often referred to as the Dory..
When 4DS receive a platform lot from IMEC they test broadly in two ways: 1. Interface to the memory controller and 2. "bypass" the memory controller and interface "directly" to the memory cell array (not quite what is going on but effectively the impact).
When PL3 was received there was a design error in the memory controller interface that meant the test chips seemed dead because they could only do 1. above. 4DS bought new testing equipment so the could test the more precisely and measure the memory array functionality and discovered (after announcing that the chips were dead) that in fact, except for the memory controller interface the chips were live and functioning well.
With the 60nm PL4 they fixed the error and were able to test the chips normally using their new equipment, and the results were outstanding - far exceeding the most optimistic projections, and everyone thought they would go to commercialisation of the tech as was always the plan (at least as publicly stated)
They then announced PL5 (at 60nm) and PL6 at 20nm. This meant a 12 month delay so SH'rs sold out to revisit closer to the release of PL5 or PL6.
Now this is where it goes a bit haywire. The market (ie we) assumed that PL5 was a tuning release at 60nm to test various configurations that were not tried in PL4 - since the most likely to succeed config were used for that as they needed a working memory array able to interact with the standard memory controller, so risks were minimised. However during the testing they could that some stuff that was theory was actually fact, and one of the big ones was the variable voltage storage response which meant each cell could reliably operate in a non-binary state (so you could store more than just 1 or 0 in a cell) they also noted that there were a bunch of ways they could vary speed, reliability, retention, duration, etc by using different configurations in the manufacturing process - in other words the cells were highly tunable, but they didn't have proper data on this (possibly because some of what they found was a result of natural variation in the cells on the platform).
My guess (because they still haven't clarified) is that PL5 was not a tuning -rerun of PL4 - which we all thought (without them explicitly saying so), but a a pure information feed for PL6 which meant they were not trying to reproduce the success of PL4 but test the extremes of configuration and understand the variance in the cells as a result of the manufacturing process. Some of it would have been a retest of the "best" PL4 configuration results but only to act as a control for the other cells. Hence the strange way the PL5 comments have been framed. PL5 was meant to tell them where too much was too much, not to tell them what was safe. Hence there is a large failure expectation in the cells and that is actually a "good" result if you are trying to make a PL6 that works. This is similar to load testing software before release - you load until destruction is reached (or you run out of bandwidth). If true then we have the first massive communication failure which could have been avoided by properly informing the SH'rs what the plan was.
Now with PL5 they are able to both see the memory controller results but also with their testing equipment what the underlying cells are actually capable of with a more appropriate memory controller (which doesn't exist yet). Why? because the memory controller is treating the cells as if the are filamentary reram, but these are a revolutionary area reram and a custom memory controller could make use of that fact and achieve far more of what the cells can actually do - possibly including the non-binary storage capability. It is also likely that a custom controller would be more fault tolerant able to write to the area rather than just an assumed filament connection point (guessing here). Hence PL5 has revealed to them that they are scratching only the very surface of the value of the tech, and slamming them up against a highly fault sensitive interfacing method making yield artificially low. My guess is that they are seeing lots of failure at the interfacing point to cells that otherwise are perfectly functional and this makes the current memory controller a major bottleneck in performance and yield.
They think all of this is too complex to explain and have thus made no attempt. Major communication mistake number 2
Lastly the plan was to sell the tech, and specifically not to try and design and develop a memory chip - just prove the tech works with a standard memory controller, but now they seem to have changed strategy to at least develop the first stages of full chip, probably for the reasons above - the story is a lot easier to sell if they can show what the thing can really do. They never discussed of explained this shift with SH'rs and it means a year or more delay on selling the tech to most people - but in reality once PL6 works it could drop at any point - particularly if they have even a design for a custom memory controller to use the full area of the area reram - so there is not really a major shift to timelines.
So I suspect PL5 was not so much of a tech failure as a communication failure, and I think this is why they never actually made a fuss about releasing "results" from PL5 and scheduled it to be right on top of PL6 - because after PL4 PL6 at 20nm was the real target and PL5 was a stepping stone needed by the techs to tune the PL6 design, it was never meant to be a published test lot in its own right - we just didn't realise that because they never clearly explained why other than to say that Pl5 would inform PL6 - which it has.
I'd say in terms of what the market expects - memory controller output, the results might seem iffy (if only because yield for each set of stats achieved is probably low) but at the tech information point for scaling down from 60 to 20nm it was probably a huge success and at the individual cell array level they have found that the variations in the config revealed a bunch of stuff they now desperately want to surface to the controller but cant with the current controller design. Again they should have been more open with the SH'rs and the price would be bouncing higher.
Now lots of the above is speculation, but it all fits with what we are seeing and the 4DS communication history - even down to the PL3 failure that a month or two later turned out not to be a failure at the level that mattered most - the memory cell array - which made PL4 almost a certain success : fix the controller interface design error and the cells were always going to fire up successfully because they had already succeeded in PL3.
This SP is a function of incredibly bad communication at almost every step, not of a loss in faith in the underlying technology. It will recover rapidly with the first correctly worded vaguely positive announcement - particularly if they address the CR issue properly, which essentially mean calling it off for the time being, or raising at the current or higher price after full disclosure rapidly.
Silence at this point is not the answer there has to be a total rethink in communication and SP management if they expect to get to the end of this.
Expand
