Ann: Company Update, page-53

From what I know, the ASIC Wafer process has a 6-12 week timeline, including testing and possibly changing one mask layer, or circuit design to iron out any bug/s.

I think that a number of company's we are allegedly dealing with are just waiting on the finished chip, but have already signed some sort of agreement with Brainchip that is hidden behind an NDA.

It's almost as if, the company knows that revenue is secured, because of pre-existing agreements that will blossom once the chip is ready for release to engineering teams...maybe that's way off the mark, but that's my take, at this stage.

I am trying to confirm the timeline mentioned above, with tapeout being confirmed yesterday, I am pretty happy that we have cleared yet another hurdle, for the doubters among us, why would Brainchip apply for an export licence to China, if we had nothing in the pipeline ?

I haven't asked any questions of Louis, just hope your questions get the respect they probably deserve.

Have a great day back in Australia....Tech