"The testing to date has successfully demonstrated that the reference memory cells on the Third Platform Lot perform similarly to the identical reference structures on the Third Non-Platform Lot, indicating
that the Lot had been manufactured properly. However, testing of the memory cells used in the imec megabit
memory array showed unexpected problems with scaling the memory cell to small dimensions suitable for Storage
Class Memory potential applications. These results suggest that the memory stack etch mask modification and
further optimization of the etch process utilizing this new mask appears to have created another problem, while
having resolved the root cause of the electrical shorting of the memory devices in the Second Platform Lot."
FFS
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2 | 205301 | 0.083 |
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1 | 100000 | 0.081 |
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