>With no capacitor, and no filament, the usual limitations dont...

>With no capacitor, and no filament, the usual limitations dont apply here. We are an area based reram, we don't rely on a filament scaling down. >We also don't rely on a capacitor that holds charge scaling down.

Plainly they can, and do:
"However, testing of the memory cells used in the imec megabit memory array showed unexpected problems with scaling the memory cell to small dimensions suitable for Storage Class Memory potential applications." - Company Update 04/08/22

Yep, and that area based effect depends on parameters that are size related as well. Its also not the memory effect itself, its the rest of the addressing etc that also has to scale. I am not saying its an issue, its something that has to be carefully managed.

A lot gets said here to brush off any possible negatives.

>There is another subsequent announcement around PL2 about scaling down to the lowest size supported by the Imec memory platform.

I've gone through the announcement, I cannot see any reference to this statement.
The IMEC Belgium fab can go down to 7nm. As far as I am aware, the IMEC memory platform is a 1MB technology at 40nm. Since its BEOL, a memory at smaller scale can be integrated with it, so not a technical problem. But there is no indication that current platform lots are smaller than 40nm that I can see.

>I could also quote announcements over three years old. But a lot happens in three years. They aren't sitting on their hands.

A lot happens in three years, that they have to inform the market about. A change in scale is a really big deal, both for risk reasons and competitive reasons. If 4DS were shooting at 7nm off the bat, a really big deal for something with NVM properties, you'd be hearing about it.