They did publish these exact words "Optimization through...

They did publish these exact words "Optimization through simulation – currently SPL >70dB @ 1m" in the AGM Presentation.
I know there was some debate at the time as to what "optimization through simulation" meant. My opinion only, is that it meant they had used their simulation tool to achieve a real world optimisation of the physical chips, which improved on the previous SPL (it was somewhere around 55dB) by about 15dB, which was then found to be measurable as over 70dB @ 1m.
I come to my opinion because we have to keep in mind that under 70dB would be a fail. 70dB is the benchmark minimum needed to have a viable single chip product for single chip applications, if the aim is to be (at full 20Hz to 20kHz frequency range) a voice coil driver substitute. A demo under this SPL does not make sense, given that they said the demo would only proceed on their having met their requirements, nor does mass production of anything less than a 70dB single chip make sense. So given that we are told demos happened, and mass production will happen via EM, then my view is they did achieve 70dB in the real world, and while they have not yet published a SPL figure on the EM website, they did publish >70dB SPL in the AGM presentation. So they sort of published something (under the radar). And yes it is disappointing that's all they have published. I wish they would definitively specify SPL on the EM website.