Hi @Cguv, the TRL's commentary is interesting & it's easy to see...

Hi @Cguv, the TRL's commentary is interesting & it's easy to see there'll be more platform lots required going forward.

4DS will need to demonstrate repeatability & improvement on PL4 results (just like the company highlighted results repeatability of their non-platform results years ago in their announcement dated 01/02/21).

There's also the unanswered questions around scaling & performance at smaller geometries. I remember when the technical update announcement landed on 17/08/21 & heaps of posters of HC started suggesting that the announcement wording "second platform lot wafers demonstrated device scaling to IMEC's minimum geometry" was referring to something less than 20nm, but as it turns out, IMEC's minimum PL geometry was much bigger at 60nm.

More manufacturing of platform lots, more testing and results required before a potential buyer is interested enough to pay $billions.

Hopefully it all works out great eventually.