Ann: Further Significant Megabit Success, page-903

@Khoutam
Hey King, et al, what do we think brother?

Uncle Pat just dropped 3D stacked cache memory on the table at 4nm and is rolling out a new 40yr generational change design in "Meteor Lake"

One wonders how? Or does one? Interesting ;-)

8tey



Intel CEO Pat Gelsinger, in the Q&A session of InnovatiON 2023 Day 1, confirmed that the company is developing 3D-stacked cache technology for its processors. The technology involves expanding the on-die last-level cache (L3 cache) of a processor with an additional SRAM die physically stacked on top, and bonded with the cache's high-bandwidth data fabric. The stacked cache operates at the same speed as the on-die cache, and so the combined cache size is visible to software as a single contiguous addressable block of cache memory.