I think iterative process actually completed. Check out this...

I think iterative process actually completed. Check out this report from TMT analytics 27/2/19

"In 2017 4DS had already demonstrated extremely high access speeds for
a non-volatile memory (NVM), i.e. close to DRAM speeds, while the individual memory cells had already been scaled down to a 40nm (nanometer) resolution in 2016.

With the number of switching cycles (endurance) into the millions, 4DS has now demonstrated endurance for its memory cells which is well in excess of what is currently required by Storage Class Memory (SCM)"

Million cycle endurance is well excess required for Storage class memory. We have now tens of millions. Speed and scale already achieved. So no more iteration required.

But why they are doing another iteration? Because they paid to use the facility until October 2019. It is logical to do another iteration to further enhance the chips (no harm is done) and also required to produce new arrays to integrate with IMEC standard carrier. Hence they are doing two sets of 23 wafers.

Integration is straightforward and very low risk. From TMT, "This platform is imec’s standard carrier for memory arrays and the integration is straightforward and very low risk."

So, we are at the very low-risk curve and really really very end to a long process. Cheers to LH.