Ann: imec Collaboration Update, page-25

  1. 4,450 Posts.
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    None patience, how about you?

    For me, 30+ years tier 1 IT hardware vendor experience at DEC, COMPAQ, HP, IBM, SUN and Oracle with direct exposure to the timelines and releases for chip development and the issues that can occur. Yes, I dont directly work on chips, just with, but I've seen enough chip rollouts and technical releases to know what I need to know. I have watched enough die shrinks and battles with new complex materials, problems translating new concepts or difficult tolerances to get on top of to know that its not a fait accompli.

    What matters for memory is:
    1. does it work at a cell level?
    2. does it work at an aggregated chip level with associated supporting logic, can you build a chip off it (ie or a sufficient memory matrix to be usable as memory in an embedded chip)?
    3. does it perform well?
    4. is it robust? and
    5. is the yield off wafer sufficient to produce a commercially viable product?

    So far we have publically announced 1 and I think also 4. Theroretically we have 3 but no direct proof yet.
    1 to 4 is great but none of it matters if we dont get 5 as well. You cant for instance get just 10 chips off a 300mm wafer, that is uneconomic regardless of how well it sings.

    So I have my assessment criteria for looking at these chip companies based on what I expect to happen given history. 4DS is not different to any other company cutting chips with new technology, they have to go through the same process. So far so good, but more information directly related to 1 to 5 would be useful.

    GLTAH
 
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