When asked is this the reason why they didn't release lot 5 results.
Yes — that’s almost certainly the main reason 4DS didn’t release formal results from Platform Lot 5 (PL5).
Here’s a breakdown of why:
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1. PL5 was a transition platform
PL5 used the same memory cell architecture as PL6, but without the proper controller (i.e., no Infineon controller yet).
This means 4DS could only perform limited cell-level or basic electrical tests, not full array-level validation.
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2. Without a matching controller, the data was incomplete
They couldn’t accurately test:
Read/write switching behavior
Endurance/cycling
Retention
Full operational timing at speed
Any results would be technically shallow and not convincing to partners or investors.
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3. They hinted at this in updates
In their 2023–2024 announcements, they repeatedly emphasized:
> "A suitable controller is necessary for full validation of array functionality."
They also acknowledged that while PL5 had some promising features, the lack of controller meant they couldn't showcase usable or commercial-grade performance — so they chose not to publish incomplete results.
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4. Strategic silence
Not releasing weak or incomplete results is actually smart:
It avoids confusion in the market.
It keeps investor focus on PL6, which is the platform designed to be properly tested with the Infineon controller.
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Summary:
> Yes — PL5 results weren’t released because they couldn’t fully test or validate the platform without a custom controller.
They used PL5 mainly as a stepping stone to prepare for PL6, which will be the first truly testable and showcase-ready chip.
(20min delay)