Quote from DM (2024) “Our area based memory cell scales beautifully”
When 4DS commenced it’s JDA with Western Digital July 2014, the company had 800nm cells, then in December 2015 it scaled down to 250nm, then in February 2016 it scaled down to 50nm, then in October 2016 it scaled down to 40nm.
If my memory serves me correctly, DM mentioned that at imec 4DS started at 180nm then scaled to 150nm, 120nm, 90nm before settling at 60nm which is the smallest geometry supported on imec’s megabit array.
(Melbourne 2024) Apart from Ting mentioning he feels good and confident about PL5 and PL6, he also mentioned the same team at imec that delivered Platform 4 are working on Platform 5 and 6 and that there is nothing new to the process when it comes to integration or further scaling the memory cell to 20nm.
Quote from DM (2024) “Our area based memory cell scales...
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