They do, per se, however typically the bleeding edge of...

They do, per se, however typically the bleeding edge of production nodes is used for processors and the like.

Storage doesn't use or need nodes that small. The worlds most cutting edge DRAM today is somewhere between 10nm - 19nm.

4DS have made cells at 40nm, IMECs MB test platform is 60nm.

This is giving the whole Xnm node argument credence too, as really its mostly a marketing tag line. Speak to genuine engineers in this space and they we all argue the nuances depending on their perspective and knowledge and most of all none of them will have a black and white view like many seem to have here.

It all started to get messy around 60nm, because judging a process by the smallest line you can etch isn't really a useful metric anymore. The pitch between lines and the pitch at which they cut into the transistors and the achievable gate density (i.e. 2-input nands/um^2) would be more telling. You can increase the density without changing the etch-able dimension with improvements in other areas too.

People only need to ask themselves a very simple question moving forward.

Is groundbreaking technology that the industry has been begging for, for more than a decade that no one else has achieved and has been fully qualified with IMEC worth AUD$240m.

If you think yes or less, sell your shares.

If you think no or more, buy shares.

Simple.