Sorry Chiro, more vomit mate... Would love to be able to talk exclusively on the subject without having to refer to industry announcements but don't have the qualifications sorry..

Samsungs revenue and capex spend seems promising however... Would love to know what the are going to spend money on??

I mean any suggestion of collaboration is all just a total coincidence IMHO... GLTAH 8tey

From the SAMSUNG QTRLY Report.. $21.7B USD & $7.6B USD respectively...

The Company’s capital expenditures in the second quarter was KRW 12.3 trillion, including KRW 10.9 trillion ($8.3B USD spent in the DS Division) and KRW 0.8 trillion in SDC. Similar to the first quarter, spending on memory was concentrated on infrastructure at P3 and on process migrations at fabs in Hwaseong, Pyeongtaek and Xi’an. Investments in the Foundry Business focused on increasing production capacity of under 5-nanometer advanced processes.

The Foundry Business achieved its highest ever second quarter revenue thanks to yield improvement, solid demand for advanced processes centering on HPC and stable demand in matured processes from various applications. It also achieved its highest second quarter profit. In addition, it has strengthened technological competitiveness through the world’s first mass production of the 3-nanometer GAA process, accomplished in June.

In the second half, the Company maintains its view that HPC and 5G-related demand will remain solid despite uncertainties related to geopolitical issues and inflation. Through close cooperation with customers, Samsung aims to exceed market growth through yield improvement of advanced processes alongside a proper pricing strategy.

In addition, the Company plans to advance the completion of second-gen GAA process development and expand customer base for large-scale orders. In October, offline forums will take place in US (WDC, INTEL, IBM), Europe (IMEC), Japan (KIOXIA) and Korea(SAMSUNG) to further strengthen customer networking.

Gate-all-around FET (GAAFET)[edit]

A gate-all-around (GAA) FET, abbreviated GAAFET, and also known as a surrounding-gate transistor (SGT),^[51][52]is similar in concept to a FinFET except that the gate material surrounds the channel region on all sides. Depending on design, gate-all-around FETs can have two or four effective gates. Gate-all-around FETs have been successfully characterized both theoretically and experimentally.^[53][54]They have also been successfully etched ontoInGaAsnanowires, which have a higherelectron mobilitythan silicon.^[55]

A gate-all-around (GAA) MOSFET was first demonstrated in 1988, by a Toshiba research team including Fujio Masuoka, Hiroshi Takato, and Kazumasa Sunouchi, who demonstrated a vertical nanowire GAAFET which they called a "surrounding gate transistor" (SGT).^[56][57][52]Masuoka, best known as the inventor offlash memory, later left Toshiba and founded Unisantis Electronics in 2004 to research surrounding-gate technology along withTohoku University.^[58]In 2006, a team of Korean researchers from theKorea Advanced Institute of Science and Technology(KAIST) and the National Nano Fab Center developed a3 nmtransistor, the world's smallestnanoelectronicdevice, based ongate-all-around(GAA) FinFET technology.^[59][25]

GAAFETs are the successor to FinFETs, as they can work at sizes below 7 nm. They were used by IBM to demonstrate5 nmprocess technology.

As of 2020, Samsung and Intel have announced plans to mass produce GAAFET transistors (specifically MBCFET transistors) while TSMC has announced that they will continue to use FinFETs in their 3nm node,^[60]despite TSMC developing GAAFET transistors.^[61]

Multi-bridge channel (MBC) FET[]

A multi-bridge channel FET (MBCFET) is similar to a GAAFET except for the use ofinstead of nanowires.MBCFET is a word mark (trademark) registered in the U.S. to Samsung Electronics.Samsung plans on mass producing MBCFET transistors at thenode for its foundry customers.Intel is also developing MBCFET "nanoribbon" transistors.

Stacked Nanosheets of Pr_1–xCa_xMnO₃(x= 0.3 and 0.49): A Ferromagnetic Two-Dimensional Material with Spontaneous Exchange Bias

• Anustup Sadhu

and Sayan Bhattacharyya^*


In this work, we demonstrate the feasibility of hybrid co-integration of a surface-engineered WSe₂-based thin film transistor (TFT) and resistive random access memories (ReRAM) to realize a 1 transistor–1 resistor (1T1R) memory cell. This is done through integrating WSe₂of different morphologies (single crystalline for TFT, and polycrystalline for ReRAM) processed through different synthesis technique, to address the conflicting charge transport attributes required for logic and memory. As TFT should be optimized for high performance and low leakage, the high-quality mechanically exfoliated WSe₂is utilized as the transistor channel. On the other hand, ReRAM should be optimized for low-voltage defect-enabled switch ability, for which solution-processed WSe₂is employed. Despite WSe₂2DMat being well investigated for future logic application, its application for 1T1R memory cell by hybrid co-integration is yet to be investigated. Moreover, our proposed processes are room temperature based, offering compelling compatibility with temperature-limited 3D monolithic process integration and flexible electronics processing. Furthermore, we propose through calibrated compact device modeling and circuit simulations that sub-0.01 µm²1T1R cells with good read/write margins are feasible by stacking 2D nanosheets to realize a multiple-stacked 2D TFTs to drive the 2D ReRAMs.

IBM and Samsung have announced a Semiconductor Breakthrough that will power Smartphone batteries for a week & much more

In late November 2020, Patently Apple posted a report titled "TSMC Reveals a Major Breakthrough Processcoming to their 2024 2nm Processors that will Power Future Apple Devices." The report noted that "In the 2nm process, TSMC will abandon the FinFET (Fin Field Effect Transistor) that has lasted for many years, and even not use the GAAFET (Surround Gate Field Effect Transistor) that Samsung plans to use on the 3nm process, that is, nanowire (nanowire), but Expand it into "MBCFET" (Multi-Bridge Channel Field Effect Transistor), that is, nanosheet based instead of nanowire as presented in the image below."

IBM and Samsung have announced a Semiconductor Breakthrough that will power Smartphone batteries for a week & much more - Patently Apple

It stands to reason that TSMC's competition had to illustrate that their roadmap too was evolving and advancing and yesterday IBM and Samsung Electronics jointly announced a breakthrough of their own in semiconductor design utilizing a new vertical transistor architecture that demonstratesa path to scaling beyond nanosheetthat has the potential to reduce energy usage by 85 percent compared to a scaled fin field-effect transistor (finFET).

Historically, transistors have been built to lie flat upon the surface of a semiconductor, with the electric current flowing laterally, or side-to-side, through them.With new Vertical Transport Field Effect Transistors, or VTFET, IBM and Samsung have successfully implemented transistors that are built perpendicular to the surface of the chip with a vertical, or up-and-down, current flow

The VTFET process addresses many barriers to performance and limitations to extend Moore's Law as chip designers attempt to pack more transistors into a fixed space. It also influences the contact points for the transistors, allowing for greater current flow with less wasted energy. Overall, the new design aims to deliver a two times improvement in performance or an 85 percent reduction in energy use as compared to scaled finFET alternatives.

Recently, IBM announced the 2 nm chip technology breakthrough which will allow a chip to fit up to 50 billion transistors in a space the size of a fingernail. VTFET innovation focuses on a whole new dimension, which offers a pathway to the continuation of Moore's Law.

The new vertical transistor breakthrough could help the semiconductor industry continue its relentless journey to deliver significant improvements, including:

• Potential device architecture that enables semiconductor device scaling to continue beyond nanosheet.
• Cell phone batteries that could go over a week without being charged, instead of days.
• Energy intensive processes, such as cryptomining operations and data encryption, could require significantly less energy and have a smaller carbon footprint.
• Continued expansion of Internet of Things (IoT) and edge devices with lower energy needs, allowing them to operate in more diverse environments like ocean buoys, autonomous vehicles, and spacecraft.

Dr. Mukesh Khare, Vice President, Hybrid Cloud and Systems, IBM Research: "Today's technology announcement is about challenging convention and rethinking how we continue to advance society and deliver new innovations that improve life, business and reduce our environmental impact. Given the constraints the industry is currently facing along multiple fronts, IBM and Samsung are demonstrating our commitment to joint innovation in semiconductor design and a shared pursuit of what we call 'hard tech."

The first chips using this new technology will be used in IBM servers. Neither IBM or Samsung provided a concrete roadmap for their next-gen chip using VTFET, likely in part due to the current chip shortage reality