Ann: Positive results achieved with 300nm 4Kb memory array cells, page-40

I have made an enquiry with the company yesterday by way of email in relation to possible concerns about errors on the 40nm and got the below positive response;

In the course of our technology development, we ran a large number of experiments and learned how to tune the technology to the stringent requirements of the semiconductor industry.

Together with Leti we were able to address the scalability issues and design a scheme which addresses the issues of nano porous irregularity so that it doesn’t affect scalability, and the conduction is not dependent on the size and uniformity of the Silicon Oxide porosity.