Metaldan I think you should read the relevant 4C paragraph again
It is somewhat ambigious, but states that wafers for both lots will be delivered in Q3
If that is the case testing results of PL5 will not be known prior to the start of PL6, which is to begin in Q2 as stated
Some processing refinements for PL5 may be relevant prior to PL6 commencement, but even that is not what's stated
So much for 4DS being open and transparent, when they throw in an ambigious statement into the 4C, which clearly people are interpreting differently to whats stated
Metaldan I think you should read the relevant 4C paragraph...
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