power/density will be optimal (commercially viable cost to volume ) at 20nm
the infineon 'platform' contract is to unlock and read pulse signal on/off values across the area of the interface to read and switch all cells independently of each other in parallel - this has been out of reach on existing platform access equipment - this if successful unlocks the ability to use different cells across the chip for different functions at the same time with statistically significant system architecture power savings (2x order of magnitude minimum) - huge step forward
question posed that what if 20nm tanks? where does the coin go that the company raised for the design contract - company can't simply keep the balance of funds raised
suggest the design contract is not dependent on 20nm alone but generic to 60 and a potentially developed 45 if needed.
without
detailed strategic pathway it is all speculation on my part
the value use case - this vid nails it imo but there is a looooong way to go yet - first Q a buyer will ask is have you met solder reflow certification / qualification 2min at 260
0? -for a premium the answer must be yes as that is one of the last chip qual points prior to commercial rediness........imo
( vid clipped to second half) - the value of this memory next next to dram/sram delivers hpc where it's needed most )
https://youtu.be/eqzB3cjgQ5E?t=581
but the company are not promoting anything yet with conviction even though the line of sight is sharpening onto this exact data choke point - that may change with a successful 20nm outcome or it may be further down the road - hard to tell yet
just my opinion - plenty of other views here as well
(20min delay)