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8.3¢ 4ds memory limited

Hopefully what they know now, is not going to affect what they...

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Ccr223

440 Posts.

126

27/02/23

15:18

Post #: 66489139
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Originally posted by mjshackl: ↑

Darren (I can't quote your post for some reason):

Well, it's progress. They have worked out a way to apply more voltage to the cells in PL3 in order to overcome the poorly conducting etch layer so they can write bits in the array. It doesn't sound like they are switching the bits in an array that could be considered acting as a memory device.

This sounds a bit like like putting in a bypass relay on the headlight circuit of my Kombi to negate the voltage drop (resistance) you can get through the ignition circuit and get the headlights to shine at full voltage. (On a Kombi the current for the headlights runs through the ignition switch)

It just confirms that, under the transistors and etch, the PCMO array is fundamentally sound. The etch isn't messing up the array, the etch itself is the problem.

Nothing with respect to developing an effective etch, although maybe this gives the team at Stanford some more options.

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Hopefully what they know now, is not going to affect what they thought needed to happen in Pl4. At least it's not idle hands sitting waiting for imec.

4DS Price at posting: 4.7¢ Sentiment: Buy Disclosure: Held
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