@dim81 re Stanford discussion was more around how work takes...

@dim81 re Stanford discussion was more around how work takes place - (10-12 iterations per year, dedicated researcher, weekly/biweekly contact with 4DS team etc) rather than what they are working on achieving in our "magic PCMO sauce" . I wished I had asked the obvious logical question - "If performance is so good that it takes IMEC chip to measure it ... how do you know if an iteration worked?". I seem to remember Wilbert commenting that we need to be able to measure write speed & endurance (DRAM like level - 10^15-10^`17) .

Reflecting now, thought that this is interesting given how up to now announcements have all been about "Read speed" & discussion at least on HC that write speed was not important if we were targeting niche applications in between DRAM & SRAM where high retention (vs NAND) / high read speed was needed (example storing maps in autonomous vehicles).

Unfortunately, we didn't have some genuine technical gurus (verses people like me asking dumb questions - like what does Ting do each day - answer he's not at Stanford pressing buttons in the lab - rather designing integration processes, coordinating Stanford / IMEC etc) in the audience to probe further.