23 August 2023 MEGABIT SUCCESS 4DS Memory Limited (ASX:4DS)...

23 August 2023 MEGABIT SUCCESS 4DS Memory Limited (ASX:4DS) (4DS) (the Company), is pleased to inform shareholders that it has successfully completed the analysis of the Fourth Platform Lot and the results obtained are significantly better than the Board and management team at 4DS were expecting. Analysis of the Fourth Platform Lot has verified that 4DS has: • Successfully incorporated its ReRAM memory cells into the imec megabit array • Validated that 4DS Interface Switching ReRAM technology is transferable from fab to fab • Demonstrated a fully functional megabit array with 4DS Interface Switching ReRAM memory cells • Demonstrated consistent read and write speeds equivalent to DRAM • Proven endurance in excess of 2 billion cycles at DRAM read and write speed on a megabit array • Demonstrated persistent memory with variable and tuneable retention. Background In an ASX announcement released on 5 October 2022, 4DS stated that the etch process had induced damage to the crystallinity of the 4DS PCMO layer resulting in the write voltage needed to program the cell exceeding the write voltage that the circuitry of the imec megabit memory array could provide. Since prior wafers had shown successful programming of cells of the same size as present in the megabit memory array, the focus would be on further optimizing the etch process to ensure both residue-free etching and no crystalline damage to the 4DS PCMO layer. On 27 February 2023 4DS announced it had undertaken a number of optimization changes which were incorporated into the schedule for manufacturing of the Fourth Platform Lot at imec. 4DS also reported that it had achieved cell operation in the megabit memory array of the Third Platform Lot utilising improved test capabilities. This allowed further exploration of optimized programming conditions with the access transistors and write circuitry of imec’s megabit memory platform. These results indicated that the 4DS Interface Switching ReRAM cells were more likely to be compatible with imec’s megabit memory platform which de-risked the testing of the Fourth Platform Lot. Megabit Array Success As a consequence of all the development activities that have taken place since 5 October 2022, the Company has now demonstrated the successful transfer of all new process improvements and learning cycles developed at the Stanford Nanofabrication Facility into imec’s megabit array. These process improvements included modification of the PCMO etch process and the composition of the memory cells, and it validated that the technology optimization is transferable from fab to fab. Page 2 of 3 4DS Memory Limited | ABN 43 145 590 110 Level 2, 50 Kings Park Road, West Perth WA 6005 PO Box 271, West Perth WA 6872 +61 8 6377 8043 | [email protected] | www.4dsmemory.com After extensive analysis 4DS has now shown for the first time a fully functioning megabit array with 60nm memory cells, access transistors and write circuitry. Within the fully functioning megabit array 4DS testing confirms: - Read and write speeds at 27 nanoseconds; - Endurance well in excess of 2 billion cycles; and - Retention is persistent and tuneable. The focus of the analysis of the megabit array has been on read/write speed and endurance. The results seen are significant as they are on a known and well understood megabit array from imec. At this time the upper limit of endurance is unknown because the Company has a finite capacity due to equipment and manpower to test the upper limit in this analysis period. Additional analysis will be done over time. Retention persistence is clearly evident but remains an addressable priority that will be driven by industry and potential strategic partners as to what level of retention might best define their strategic and commercial plans. As such, robust retention testing was not prioritized in this test cycle. 4DS’ goal has always been to look to take advantage of the uniqueness of its technology as an area-based ReRAM. imec’s megabit arrays have a lower limit of 60nm for a memory cell but 4DS testing has demonstrated that our ReRAM scales consistently across available cell geometries on megabit arrays. The read/write speed and endurance parameters are critical to the Company’s goals in the memory space requiring DRAM-like performance characteristics. 4DS’ ReRAM performance profile to suitably meet this goal has been clearly demonstrated on the Fourth Platform Lot. Chief Technology Officer Mr Ting Yen stated “We are very pleased with our imec collaboration and their comprehensive engineering support that made this significant achievement possible. We would like to thank imec for keeping a focussed engineering and fab effort throughout the fabrication of this megabit array and completing on schedule.” Mr Yen further stated, “These significant and robust results validate 4DS’ optimization strategy and the decision to establish a duplicate of imec’s custom testing hardware and software for the megabit array at the 4DS Fremont facility.” Interim Executive Chairman Mr David McAuliffe stated “These megabit array results are a turning point for the Company and will now shape the Board’s strategic planning over the coming months. I would like to congratulate both the 4DS and imec teams on achieving this milestone and thank shareholders for their continued support.” Over the coming weeks additional analysis of the megabit array will continue and a meeting is being scheduled with imec in early October to discuss strategic plans. ENDS Authorised for release by the Board. Contact information Investors: David McAuliffe Interim Executive Chairman 4DS Memory +61 408 994 313 [email protected]