I am somewhat confused by this. But lately I've had a few pauses...

I am somewhat confused by this. But lately I've had a few pauses with the announcements.

Didnt we produce working chips off the 1MB wafer a long while back and then fully package them? I remember the pictures. That must have meant address lines and selectors and ...., otherwise how would they have tested them. That is now a long time ago and by definition they were "discrete chips".

We then got the embedded call from our SK partner, and they were spending considerable time developing interfaces for that/those use cases. Surely that needs a "selector" as well?

XTX are ahead of their validation by 4 months. The indication was that we'd likely get to market with this first, implying an actual product by the end of the year. I assumed discrete, because this is XTX's main gain. Is this not the case? If not, why is the memory interfacing here not been raised as an issue?

Now we here Leti, who'd know this interfacing backwards, are working with us to yield discrete chips mid 2021.

I find all this a little hard to get into perspective give then overlap and conflicting positions here.