'As such, we focus not only on the performance of the ReRAM...

'As such, we focus not only on the performance of the ReRAM array, but also use a broad range of smart engineering techniques in the Weebit ReRAM module which surrounds our memory array, to maximize that performance.' attribution Ilan Sever as per previous post

essentially the dual switch reram array optimisation is ongoing and is developing in unison with solutions that speed / maximise data flow management inputs and output with the result being time and energy to optimal operating performance hugely reduced....$$$$
= removing performance bottlenecks that are currently choking existing data management systems where that performance outcome is delayed or obscured .....yep its every MCU pretty much....( suspect it is customer specific as @Waiks stated we only know what we know for now)

The intrinsic value the collective experience of this management team is starting to really float to the top now...

every system engineer in any electronics company involved with MCUs' understands this is a must solve issue .... across every electronic market segment ......ultimately you are limited by the performance of your equipment - optimise that equipment and you optimise outcomes which in turn captures market and volume.

apply the ACS DVRP to data flow management in array architecture and the surrounding module and you optimise these system outcomes ( the ant colony system is the industry go to funnily enough - these guys are taking it to a whole new level imo )

Dadi has been here defore with Intel pentium - it was his ( and his teams) breakthrough baby back in the day ......I suspect he and this wbt team are about to do it again in micro controllers with this nvm reram ....stunning stuff from Weebit

pentium back in the day apply these exact principles




Opportunity is knocking very loudly now at the company door I suspect
happy to be corrected - aimo as always