Ann: Weebit signs first commercial deal with US-based SkyWater, page-413

@hashtagyolo

Not the easiest question to answer #yolo.You already know the original latency numbers from before, that largely pertains to the cell design and is unlikely to have changed greatly. Are you asking write latency or read latency as well? Lets just say "good enough" in both cases.

Useful latency is a function of the cell but its also a function of the selector used, the multibit capability and the way the data is delivered in serial or parallel. A lot of comparisons you see at present will be based purely on the expectations for the individual cell storing and reading a single bit.

We know it reads and writes faster than flash at the cell level for single ins and outs. You know that already. We dont know the numbers for multibit yet or in a more complex stack. If we deliver multibit in a similar latency to single bit and stack efficiently then its completely game on here.

Given our partner Leti has state of the art selector and stacking expertise, and know how to deliver, we can be pretty confident of efficiency at the whole array level as well as how the cell performs.

You need a product engineering mindset to succeed here, not a purely R&D mindset that focuses on one part of the memory array only. Focusing just on the cell is like building the best car motor and forgetting about the brakes and steering or the process and tools to build it.

I am confident WBT management have a very good holistic view on this.