CXO888 / any other attendees, page-11

I don't think that is the implication at all.

Before they went to IMEC, they genuinely thought the product's best use case was Storage Class Memory. Something not quite as fast as DRAM, but with retention, to hold all the non dynamic/changing data (such as basemap data and satellite layers for Google maps) that currently gets put in DRAM constantly requiring refresh.

A number of things have happened since then:

Full PCMO has been achieved and speeds now exceed DRAM, with some persistence. At 60 nm, whilst DRAM is scrabbling for marginal gains around the 10 nm node size.

If the convention holds, scaling down to 20nm should yield further performance gains.

20 nm is 1/9th the area of 60 nm. That implies that to switch a cell, the energy required to write the cell should be ~11% of a 60 nm cell. That is, if things scale linearly with area. Speed should increase too.

Engineers prefer simplicity. Adding another memory layer, with all the additional controls and software required to make it work in a system is not simplicity.

So why not shoot for a DRAM replacement, that is cheaper to fabricate, can achieve higher densities through stacking and has some persistence, meaning it uses less energy?