We know that reducing node size typically increases speed/reduces latency and reduces power consumption.
Perhaps they will aim for a "tune down" of the speed in the 20nm lot to match what they have in 60nm, but increases retention. This is all speculation based on the sort of mindset on experimentation I would be thinking about, but getting decent retention would be the killer blow.
The fact is the tech can outperform DRAM at 60 nm now. I'm keen to see where 20 nm goes.
CXO888 / any other attendees, page-67
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