CXO888 / any other attendees, page-70

the caution exists for another reason already witnessed at 40nm
tuneability = cell currents scales with the geometry
the company / IMEC incorporate smaller cell sizes that yield lower cell currents which technically will allow higher densities
lower cell current also means longer latency - the company ( specifically guido ) 'tuned' the cell currents to meet dram in the higher density at 40nm - this solves the need for error correction code but there was still work to do characterising current to area optimisation

traditionally latency is the value of the inherent memory latency combined with the time to detect stored values
aka
https://www.crucial.com/articles/about-memory/difference-between-speed-and-latency

so mask / etch designs proven at 60 which was the aim of the game - given failure pull it apart implement changes and get it fixed
now back in at 60 to implement design changes of the current / area work just completed that delivered the great metrics -with most likley the process improvements intended be the 'meltdown' occurred

and take those improvements into 20 to see if it scales in both manufacturability and functionality.

they can't discuss retention because they don't have any yet - they have an idea about it but nothing else yet

its essentially back to the future to characterise these adjustments in a working 20nm node with a reasonable number on retention ....doesn't have to be big at all - must be stable with all irregularities removed

@Denofiniquity1
this alone would allow a x2 order of magnitude cost saving on energy use as an example and that alone makes it a very appealing technology for immediate adoption by a big boy