Thanks @caredes well found and thanks for posting for everyone...

Thanks @caredes well found and thanks for posting for everyone to appreciate.

This is clearly designed specifically for our current chip. I assume it is the at-line testing hardware described in earlier announcements that was being developed and installed. I assume it is designed for the unpackaged chip, as I expect the probes would not work though the cover. It has to be done either on the wafer or on the die or chip before the cover is applied. The reference to the way it powers the chip implies that it is exercising it between its two extreme positions. The functional testing of the chip only requires the on / off operation from up to down position extremes. Each pixel will have to operate to precise specifications of movement and timing so each behaves identically. These are the basis of it being able to be driven by the ASIC to create audio by DSR. I like it a lot!