@uiux
Hi ui,
Great work!
Intel are claiming on-chip learning for loihi 2, but, reading their blurb, this still sounds pretty aspirational:
https://download.intel.com/newsroom/2021/new-technologies/neuromorphic-computing-loihi-2-brief.pdf
.
https://www.intel.com/content/www/us/en/newsroom/news/intel-unveils-neuromorphic-loihi-2-lava-software.html
September 30, 2021
"Investigators at Los Alamos National Laboratory have been using the Loihi neuromorphic platform to investigate the trade-offs between quantum and neuromorphic computing, as well as implementing learning processes on-chip,” said Dr. Gerd J. Kunde, staff scientist, Los Alamos National Laboratory. “This research has shown some exciting equivalences between spiking neural networks and quantum annealing approaches for solving hard optimization problems. We have also demonstrated that the backpropagation algorithm, a foundational building block for training neural networks and previously believed not to be implementable on neuromorphic architectures, can be realized efficiently on Loihi. Our team is excited to continue this research with the second generation Loihi 2 chip."
Most of Intel's patents at the NPU level are directed to analog neurons (memristor/reram), although they did have an abortive attempt to claim a digital version (note the parenthesised reference to "digital"):
US2018174028A1 SPARSE CODING USING NEUROMORPHIC COMPUTING
[0040] In one example implementation, a neuromorphic processor may adopt a “digital” implementation that diverts from other processors adopting more “analog” or “isomorphic” neuromorphic approaches. For instance, a digital implementation may implement the integration of synaptic current using digital adder and multiplier circuits, as opposed to the analog isomorphic neuromorphic approaches that accumulate charge on capacitors in an electrically analogous manner to how neurons accumulate synaptic charge on their lipid membranes. The accumulated synaptic charge may be stored, for instance, for each neuron in local memory of the corresponding core.
This application was abandoned in USPTO due to (non-Akida) prior publications.
An example of an Intel analog NPU with machine learning is found in:
US10878313B2 Post synaptic potential-based learning rule
Fig 5 illustrates an example of an analog spike and the threshold voltage levels VREFH, VREFL which are required to identify a valid spike.
A number of such spikes are accumulated to cause a neuron to fire. The comparatively narrow voltage threshold band may be more susceptible to random voltage interference and manufacturing variation than a digital bit. However, it seems that Intel may have overcome these variables.
This Intel patent illustrates the manufacturing complexities of some of Intel's neuromorphic concepts:
ELECTRONIC NEURAL NETWORK CIRCUIT HAVING A RESISTANCE BASED LEARNING RULE CIRCUIT
Examples of Intel learning rule circuits: 
501 implements the inhibitory synapse for the learning rule circuit 504 while circuitry 502 implements the excitory synapse for the learning rule circuit 504. That is, if the learning rule circuit 504 is to implement an inhibitory learning rule, channel 501 is selected by multiplexer 509. By contrast, if the learning rule circuit 504 is to implement an excitory learning rule, channel 502 is selected by multiplexer 509. Recall that, e.g., a value in a register, may establish the appropriate learning rule and provide an input signal to the learning rule circuit to indicate which learning rule is to be applied.
A
ccording to the learning rule circuit of Fig. 5, the resistance of the MTJ device 503 is measured by driving a current through the device 503, measuring the voltage across the device 503 with an A/D converter 507 and dividing the measured voltage by the measured current with logic circuit 508 
MTJ is a magnetic tunneling junction - can't make these in standard CMOS.
This is another Intel memristor/reram patent purporting to implement unsupervised learning:
US10565500B2 Unsupervised learning using neuromorphiccomputing I think due respect is due to Intel for their heroic efforts in advancing analog NNs.
Given Intel's persistance with memristor/reram, their designs may avoid some, but not all, BrainChip patent claims, but in what, in my opinion. is a less elegant solution.
(20min delay)