https://www.sbir.gov/sbirsearch/detail/1882591Phase I, will:...

https://www.sbir.gov/sbirsearch/detail/1882591

Phase I, will: Understand the operation of Brainchiprsquo;s IP Understand 28nm instantiation of that IP (Akida) Evaluate radiation vulnerability of different parts of the IP through the Akida Development Environment Define architecture of target IC Define how HARDSILreg; will be used to harden each chosen IP block Choose a target CMOS node (likely 28nm) and create a plan to design and fabricate the IC in that node, including defining the HARDSILreg; process modules for this baseline process Define the radiation testing plan to establish the radiation robustness of the ICSuccessfully accomplishing these objectives:Establishes the feasibility of creating a useful, radiation-hardened product IC with embedded NPU and already-existing supporting software ecosystem to allow rapid adoption and productive use within NASA and the Space community.\n\n\n\n\t Creates the basis for an executable Phase II proposal and path towards fabrication of the processor.\n\n