the connection between these 2 posts above is maybe not obvious
replacing the ots transistor with GSSN layer sandwiched between 2 carbon electrodes to act as the selector allows the memory array to be constructed directly on top of the silicon substrate significantly reducing cell footprint and allowing 3D stacking to occur. - related circuitry can now also be placed beneath the array - another major benefit.
3DXP was the first transistor less memory of note followed by Crossbar
this 'wbt - cea leti' work commenced in 2022 and the fact that the application patent priority date appeared last month possibly suggests significant progress has been made.
just my opinion
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