@Patchspike agree emass soc runs fine grained power gating which provides reduced power consumption by partitioning memory cell area and selectively turning off 'cells' within the memory based on use priority and inactivity. Weebit GSSN ots array selector matches this power gating functionality perfectly and explains its development and recent patent updates.
this allows wbt rram to 3D stack at scale with emass soc and interleaved silicon via.( zero latency memory + compute)
Such a configuration of memory in compute at scale is edge agnostic and best in class imo
I'm guessing we'll see what this all looks like later this year just my opinion as always dyor
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