JFS3-5 - 12:10 On Chip Customized Learning on Resistive Memory...

JFS3-5 - 12:10
On Chip Customized Learning on Resistive Memory Technology for Secure Edge AI, M. Pallo*, **, S. D'Agostino**, M.
Piccoli**, ***, D. E. Bonnet**, N. Castellani**, G. Piccolboni*, M. A. Iftakher***, J.-F. Nodin**, F. Andrieu**, D. Querlioz***, G. Molas*,
L. Hutin** and E. Vianello**, *Weebit Nano FR, **CEA-LETI and ***CNRS (Centre national de la recherche scientifique), France
This paper presents the first experimental demonstration of few-shot on-chip training on an in-memory computing resistive
memory (ReRAM) platform. We use the Model- Agnostic Meta-Learning (MAML) algorithm to reduce training iterations and
associated ReRAM conductance updates by orders of magnitude. Through co-optimization of device programming conditions
and the algorithm, we achieve >97% accuracy on the Omniglot dataset after just five training iterations (i.e., ReRAM
programming operations) while improving device retention at 150°C

Lots happening in Kyoto.............hope we can stand out a bit
VLSI2025_Advanceprogram0606-3.pdf