Wilbert made these comments about endurance needing to be higher than DRAM ( if we are going to knock DRAM off its perch), prior to knowing the 'retention' metrics that have been achieved. I am not going to do the maths but imagine if you don't need to cycle the chip every 64 micro seconds like DRAM has to, just to retain the data and you are now able to cycle it ( for example ........once every minute).
Having retention for even a minute has a mind blowing impact on lowering the number of cycles the chip has to complete to even to retain the data. I am not talking about accessing the memory for the data recovery here. Remember this is not a 'processor chip' it is 'memory' designed for storage where the data does not necessarily need to be accessed constantly to retrieve data.
Now imagine, if we have retention of a week, month , year or multiple years like Flash but with write speeds 3x faster than DRAM and DRAM like read speed.
The reality is we don't know what our retention is. DM has only said it doesn't need to be years !
Cycling requirements are obviously dependant on the 'use' for which the memory is being used, but retention is I think the KEY metric for our success and is the reason why we are trying to develop this NON-Volatile memory in the first place. Filling the gap betweenNAND/Flash and DRAM. Mixed with retention, our speed and endurance results may now challenge the DRAM market How big a challenge we still don't know.
In the meantime ....we continue our journey as mushrooms .
Add to My Watchlist
What is My Watchlist?
