4DS, in collaboration with imec, successfully created the Fourth Platform Lot, (PL4), after technical issues, relating to the PL3 and the imec megabit array, were discovered.
Initial testing of the PL4 revealed read and write speed at 27.0 nanoseconds, (announced on 23 August 2023).
Further testing, with better equipment, resulted in the 18 September announcement of a read speed of 9.5 nanoseconds.
More testing revealed a read speed of 4.7 nanoseconds. (ASX Announcement on 5 February).
The latest read speed result, (a nearly sixfold improvement), has been described as amazing.
What seems to be missing from this is detailed explanations for the improvements in speeds between the PL3 and PL4.
To me the above begs a question.
Were there patent-able technical changes made in the design and fabrication of PL4 which can explain the latest quoted read speed?
It would be nice to know from Yen Ting, (CTO), if the work of imec and 4DS, over the last year or so, might result in further patents for 4DS?
4DS, in collaboration with imec, successfully created the Fourth...
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