Much like the end of Moore’s Law, the scaling challenges of flash memory have been a significant issue for several years. Embedded flash memory is reaching its limits as technology nodes for embedded applications shrink below 28nm, necessitating the reduction in the physical size of flash memory cells.
This miniaturization challenges the basic mechanism of charge trapping found in flash and other non-volatile memory (NVM) derivatives, making manufacturing at these smaller nodes extremely expensive and impractical for embedded applications.
Additionally, even at nodes where embedded flash is viable, flash memory cells have limited endurance; they can only withstand a limited number of program/erase cycles before degradation occurs.
Flash also consumes more power than alternative NVM technologies like MRAM and ReRAM. Power consumption is a critical factor in embedded systems where energy efficiency is essential for extending battery-life. In the case of power management and other high-voltage applications, customers are using a BCD (Bipolar-CMOS-DMOS) process flow that is far more sensitive to modifications in the FEOL (Front End of Line), such as those required by flash. Power devices tend to be more cost sensitive, and flash, typically requiring 10 extra masks, is very expensive to manufacture, adding 20-25% added wafer cost.
However, emerging NVMs like MRAM and ReRAM offer advantages that align better with the requirements of advanced embedded systems at smaller process nodes. These technologies also threaten to disrupt the market for embedded flash at more mature geometries, such as 40nm, 65nm, and even 130nm. This is significant for many vendors, especially in mature nodes, which are highly price sensitive.
MRAM (Magnetoresistive Random Access Memory) has gained attention for its non-volatile characteristics, high-speed operation, and durability. Companies like Everspin Technologies have successfully specialized in MRAM, which comes in various types such as Toggle MRAM and Spin-Transfer Torque MRAM.
Typically, MRAM cells consist of two magnetic layers: one with fixed magnetization and another with free magnetization that can switch its orientation. Writing data involves applying a current to generate a magnetic field, causing the free magnetization layer to align either parallel or antiparallel to the fixed layer, representing binary 1 or 0.
However, MRAM faces cost challenges due to the many thin layers required in its manufacturing process which generally add 30-40% to wafer cost. Potential contamination issues necessitate special cleanroom practices, dedicated tools, and comprehensive quality control measures, often requiring separate facilities and lines for MRAM production, further increasing costs.
Additionally, magnetic fields such as wireless chargers and automatic door locks can interfere with nearby components in ICs, posing challenges for MRAM integration, including security risks. Some leading consumer electronics companies have reportedly refused to consider MRAM solutions due to such interference issues. Other challenges include the use of rare earth materials, making MRAM expensive and creating corporate ESG issues and supply-related risks.
Another emerging memory technology is ReRAM (Resistive Random Access Memory), which has been championed by TSMC, UMC and independent ReRAM IP providers like Weebit Nano. ReRAM operates based on the resistance-switching properties of materials. ReRAM cells consist of a thin insulating layer sandwiched between two electrodes.
Figure 1: ReRAM bitcell representation. (Image: Weebit Nano)Writing data involves applying a directional voltage pulse across the electrodes, causing the creation or dissolvement of a conductive filament within the insulating layer. This change alters the cell’s resistance from a high-resistive state (HRS) representing binary 0 to a low-resistive state (LRS) representing binary 1, and vice versa. Reading data involves measuring the cell’s resistance by applying low voltage.
Figure 2: Low-resistive state and high resistive state in Weebit ReRAM. (Image: Weebit Nano)Compared to other embedded NVMs, ReRAM technology requires fewer additional masks to manufacture. For instance, Weebit Nano’s ReRAM needs only two additional masks, compared to typically 10 for flash, equating to less than 10% added wafer cost. And, unlike MRAM, ReRAM isn’t susceptible to magnetic fields. It is also naturally radiation tolerant.
Like flash, ReRAM is non-volatile, offers fast read and write speeds, and consumes very low power, making it suitable for energy-efficient applications. Programming flash memory involves erasing complete sectors before writing, leading to time and power consumption issues. ReRAM, being byte-addressable or bit-addressable, eliminates the need for an erase cycle, enhancing performance and endurance for advanced applications.
Despite the benefits, not every design start uses MRAM or ReRAM today. Partly this is due to designers’ familiarity with external flash. Though inelegant, insecure, and inefficient, it’s already in use, and there’s a ‘don’t mess with what works’ mindset among engineers.
However, the potential for widespread adoption of new memory technology is high due to partnerships with foundries and interest from various industries. The main drivers are smaller process nodes where incumbent solutions aren’t available, and power management designs in older nodes. This trend supports integrating analog, RF, power management, and microcontrollers with NVM on a single chip.
More foundries are adding ReRAM capability in particular and signing up customers even ahead of full qualification. We can expect ReRAM to appear in many new devices within 18 to 24 months, replacing embedded flash and external NVM chips, and enabling cost-effective and power-efficient system integration.
Eran Briman, VP of marketing and business development atWeebit Nano, has nearly 30 years of experience in the semiconductor IP field. He leads the company’s ReRAM commercialization efforts. Prior to joining Weebit in 2020, he at Corephotonics, an imaging IP startup that pioneered the multi-aperture domain in mobile devices and was acquired by Samsung Electronics in 2019. Before that, he was at CEVA where he helped to shape the company as a leader in numerous DSP markets including mobile, IoT, surveillance, infrastructure and automotive. He also held engineering and engineering management roles at DSP Group, where he led large development teams. Eran holds a B.Sc. in electrical engineering from Tel Aviv University and an MBA from the Kellogg Business School at Northwestern University. He holds several patents in and has authored numerous technical publications.
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