I didn't know they had testing stacking already got a link?"The...

I didn't know they had testing stacking already got a link?

"The combination of Weebit ReRAM and Leti’s BEOL selector reduces the memory bit size by ~10X."

assuming each product cycle is 2 years (1 year design, 6 months ordering & producing, 6 months testing), maybe things can be done in parallel, i dunno...
Of course I'm making guesses....as there is little to go on, takes but my estimations are as follows:

Year 0: Demo Chip - 8Mb (Soc, not discrete)
Year 1 : Weebit not concentrating on Discrete ????
Year 2 : Weebit not concentrating on Discrete ?????
Year 3 : Design Gen 1 : 256 Mb - 1S1R - Single Layer
Year 4 : Produce & Test Gen1
Year 5 : Design Gen 2 : 2,048 Mb (2Gb)- 8 Layer
Year 6 : Produce & Test Gen 2
Year 7 : Design Gen 3 : 32,768 Mb (32Gb)- 128 Layer
Year 8 : Produce & Test Gen 3
Year 9 : Design Gen 4 : 262,144 Mb (~256 Gb) 256 layer with 4 Bit multi layer
Year 10 : Produce & Test Gen 4
Year 11 : Design Gen 5 : 1,048,576 Mb (1 Tb Gb) 512 layer with 8 Bit multi layer
Year 12 : Produce & Test Gen 5 $$$$$


just my thoughts.....