Sorry guys, I actually I made some big mistakes in my last post.
"Let's say for a given ReRAM geometry you get a single bit into a square100nm x 100nm. That's 1.0 x 10-14 m2, or 1.0 x 10-8 mm2, or 100 x 106 bits/mm2."
From what I've since read, this is about the packing density of the 7nm node, so perhaps a bit over-optimistic for the future, and we certainly are not there yet. We probably need to at least double the dimensions (to 200nm) achieving only 1/4 the density - then equal to 25 x 106 bits/mm2.
However I also made a 103 error in my next calculation: "If we stack 10 layers, allowing 100nm per layer, then we arrive at the same packing density as the crystal memory, of 1 Gbit/mm3."
10 layers at 100nm per layer comes to 1 µm thicknes (1/000th of a mm), so we would get 10,000 layers (yealding a packing density by my earlier assumptions, of 1,000 Gbit/mm3). If we also double the thickness of our layers we can still stack 5,000 layers in a 1mm thickness.
Combining our new calculations of planer packing density and stacking layers, we arrive at 25 x 106 bits/mm2 x 5,000 layers/mm = 1.25 x 1011 or 125 Gb/mm3.
Of course it won't be feasible to stack 5,000 layers any time soon, but 40 layers already gets us to 1 Gbit/mm2 of chip area.
However you cut it, This crystal memory is not a starter.
All IMO.
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