Well, if that's what Coby has said, then I would obviously have...

Well, if that's what Coby has said, then I would obviously have to defer to his far greater expertise. I was just going on material I have read about ReRAM in general, plus electron microscopy images I've seen of the nano-pores, which appear to be several nm across and randomly distributed across the surface.

Perhaps WBT have developed manufacturing techniques that control the size and location/distribution of the nano-pores.

However, once they achieve 22nm, I would think the quickest path from there, to higher packing densities, would be to move to 3D layering. This is how the capacities of flash chips have continued to increase. However, I think multi-layering of flash may soon come up against power dissipation limitations. WBT's ReRAM would lend itself much better to this approach, due to it's simpler architecture and 2 orders of ten lower power dissipation.