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Originally posted by bluebrando: ↑

Hmmm ... Is GlobalFoundries the Tier 1 fab that taped out our 22nm chip given the following info I came across on another chat forum?
Foundries Prepare For Battle At 22nm ...

But choosing one 22nm technology from a given foundry may be far different than 22nm at a different foundry. There are three different versions of 22nm being rolled out by different foundries:
TSMC and UMC are developing a 22nm planar bulk CMOS process.
GlobalFoundries is gearing up a 22nm planar FD-SOItechnology.
Intel is pushing a low-power 22nm finFET technology.

From the WBT announcement of 3rd Jan:

"Weebit Nano Limited(ASX:WBT,Weebitorthe Company), a leading developer of next-generation memory technologies for the global semiconductor industry, has taped-out (released to manufacturing) demonstration chips integrating its embedded Resistive Random-Access Memory (ReRAM) module in an advanced 22nm FD-SOI (fully depleted silicon on insulator) process technology."

https://semiengineering.com/foundries-prepare-for-battle-at-22nm/

Excerpt from the article of November 2018:

FD-SOI
GlobalFoundries was the first player to enter the 22nm race. Three years ago the company introduced a 22nm FD-SOI technology. For some time, Samsung has offered 28nm FD-SOI with an 18nm version in the works.

In addition, GlobalFoundries is developing a 12nm planar version of FD-SOI, which is expected to appear in 2022. Generally, 22nm or 18nm FD-SOI doesn’t compete with 16nm/14nm finFETs, and they serve different markets with little overlap.

FD-SOI uses a specialized SOI wafer, which integrates a thin insulating layer (20 to 25nm thick) in the substrate. This layer isolates the transistor from the substrate, thereby blocking the leakage in the device.

FD-SOI also is based on a planar, fully depleted architecture. “This essentially eliminates the random dopant fluctuation, providing superior mismatch and electrostatics to improve sub-threshold slope,” GlobalFoundries’ Schaeffer said.

GlobalFoundries’ 22nm FD-SOI technology, called 22FDX, incorporates high-k/metal-gate with silicon-germanium in the channel. It provides 30% higher performance and 45% lower power compared to 28nm. It was production-qualified in early 2017.

Recently, GlobalFoundries added more capabilities to the mix. “Sub-6GHz RF, mmWave, ultra-low leakage and ultra-low power extensions have all been qualified,” Schaeffer said.

What makes FD-SOI attractive are two features—low-power and body bias. It enables drive currents of 910μA/μm (856μA/μm) at 0.8 volts, with voltage operations down to 0.4 volts.

“Body bias is the ability to fully control the threshold voltage (Vth) of the transistors dynamically by polarizing the back gate of the transistor. Vth—which was a parameter determinable only by process through complex doping techniques—is now programmable dynamically through software,” said Manuel Sellier, product marketing manager at Soitec. “Designers can use this feature to dynamically manage the leakage in their circuit, and also to compensate static (process) and dynamic variations (temperature, voltage, and aging) efficiently. The result is a 4X to 7X energy efficiency gain at ultra-low power.”

FD-SOI also supports forward body biasing. When polarization of the substrate is positive, the transistor can be switched faster, according to STMicroelectronics.

FD-SOI, however, has three drawbacks—cost, ecosystem and adoption. For years, FD-SOI has had limited adoption. Intel, TSMC, UMC and others have never adopted FD-SOI, saying bulk CMOS enables high-performance devices at better costs. For example, an SOI wafer sells from $370 to $400 each, compared to $100 to $120 for a bulk CMOS wafer.

But FD-SOI does have a lower mask count, which compensates for the wafer cost. FD-SOI has 22 to 24 mask steps, while a comparable bulk CMOS process has 27 to 29 mask steps, according to IBS.

FD-SOI is closing the gap, too. “We are now looking at what we view as the limit of bulk CMOS,” IBS’ Jones said. “Transistor costs for 22nm FD-SOI are within 5% of the transistor costs for 22nm HKMG (high-k/metal-gate). 22nm FD SOI gives 30% to 50% lower power consumption compared to 22nm HKMG, which is important for wearable and IoT devices.”

The FD-SOI community, however, lags in terms of the EDA/IP ecosystem. “The IP ecosystem for 22nm FD-SOI is strengthening, but 22nm HKMG bulk CMOS has a broader IP ecosystem,” Jones said.

The tide is turning. Cadence, Mentor and Synopsys have been certified for various EDA tools for GlobalFoundries’ FD-SOI technology.

“There are some unique capabilities for RF, for example, with integrated FD-SOI, which are very hard to equal in other ways,” said Wally Rhines, president and CEO of Mentor.

FD-SOI has other advantages. “While the finFET gives you near zero leakage, you still have dynamic power. One of the advantages of FD-SOI is dynamic power. If you can reduce the voltage from one volt down to 0.6, that’s a 65% reduction in power. FD-SOI has some advantages in being able to dynamically alter the power versus the performance balance,” Rhines said.

Expand

looks bang on

I saw an article that suggests it is https://www.eenewseurope.com/en/weebit-tapes-out-reram-on-22nm-fdsoi-process/

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looks bang on I saw an article that suggests it is...

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