1) 2025 Symposium on VLSI Technology and Circuits, Kyoto, Japan
Technology / Circuits Joint Focus Session 3
JFS3 AI and ML Hardware
Thursday, June 12, 10:30-12:35
JFS3-5 - 12:10On Chip Customized Learning on Resistive Memory Technology for Secure Edge AI, M. Pallo*, **, S. D'Agostino**, M. Piccoli**, ***, D. E. Bonnet**, N. Castellani**, G. Piccolboni*, M. A. Iftakher***, J.-F. Nodin**, F. Andrieu**, D. Querlioz***, G. Molas*, L. Hutin** and E. Vianello**, *Weebit Nano FR, **CEA-LETI and ***CNRS (Centre national de la recherche scientifique), France
This paper presents the first experimental demonstration of few-shot on-chip training on an in-memory computing resistive memory (ReRAM) platform. We use the Model- Agnostic Meta-Learning (MAML) algorithm to reduce training iterations and associated ReRAM conductance updates by orders of magnitude. Through co-optimization of device programming conditions and the algorithm, we achieve >97% accuracy on the Omniglot dataset after just five training iterations (i.e., ReRAM programming operations) while improving device retention at 150°C.
This paper, presented last Thursday in Japan, is now available on the WBT website
https://www.weebit-nano.com/technology/resources/
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