"... Look at the time lines. Did AKP have access to fabs to...

"... Look at the time lines. Did AKP have access to fabs to incorporate the design changes?No or they have not told us. The performance improvements are simulated imho. ..."

"... What have I posted that is not true? ..."

I completely disagree. Everything they have said indicates that they have had access to TowerJazz fab on an ongoing basis. TJ have been often been credited as being very helpful to AP. Let's look at your comments.

Timelines:

e.g. from the 2019 AGM:

Notwithstanding our recent disappointment that an unforeseen computer crash forced the temporary interruption of our acoustic testing; this past year has seen many significant accomplishments. Undoubtedly the most significant accomplishment is that we, together with our fabrication partner Tower Semiconductor, appear to have finally completed the development and fabrication process of devices that reliably adhere to the required electro mechanical performance specifications.

Similar comments ts were made in intervening announcements. Even in March 2021 they stated that they had made full structures and advanced them through to completion. As far as I can see these were the beta (60 dB) versions that followed the alpha <50 dB versions of July 2020. That follows on from the comments made in April 2020 below, referring to its fabrication partners and stakeholders in Israel, and that almost certainly refers to TowerJazz.

1 April 2020

Israel has taken some of the farthest-reaching measures of any country in the world to slow the advance of the new coronavirus. As a result, our business continuity plans have been in motion for weeks. We rapidly implemented the very best of available technologies, so as to enable our workforce to remain productive while maintaining strict compliance with government regulations and health guidelines. We have also been contending with the limitations of our fabrication partners, each facing their own evolving constraints, as established in their own regions.

We are pleased to inform that despite many obstacles, the incredible dedication and adaptability exhibited by all key stakeholders has allowed for the delivery on March 30, 2020 of the initial batch of wafers.

15 April 2020
Market Update – Progress Report
We are pleased to provide an update to the recent Announcement of 30 March 2020 that informed of the completion of fabrication, and commencement of testing of first wafers that incorporated design changes to the MEMS structure and its manufacturing process.
We are very pleased to advise that the testing conducted to-date confirms that the changes made to the design have returned the devices to electromechanical compliance. As was anticipated, the return to compliance resulted in substantive and dramatic improvement to the acoustic output of the devices.
The remaining steps required, prior to publication of performance specifications, are metrological inspection and statistical verification. Metrological inspection is critical to confirm that the manufacturing process maintains compliance to specifications while statistical verification characterizes performance on different and larger numbers of wafers.
Wafers for both purposes are currently being held by the vendor at the very last stages of fabrication. Completion of fabrication of additional wafers is expected to resume upon relaxation by the Israeli Government of work related COVID-19 restrictions, We will advise the market once the restrictions in Israel have been eased to allow the process to continue and additional wafers have been received.
This announcement has been authorized for release to ASX by Fred Bart, Chairman

30 March 2021

Market Update – Progress Report

Management is pleased to inform its shareholders that the company has produced both individual chips, and multi-chip boards that operate and play outside of the cleanroom.

As described in our 6 October 2020 market update, the primary objective of this development phase was to advance the technology so that devices can operate outside the confines of the cleanroom in its intended real-world environment.

1. The package has proven to protect the MEMS from the environment (dust particles, humidity etc.) with minimal acoustic attenuation, while providing an industry standard electrical interface.

2. The current setup operates up to 4 chips in parallel demonstrating the scalability of the technology.

3. Older versions of the MEMS chip were utilized for the first batches of packaged chips, as the iterative development process required large number of chips to be damaged during the packaging development and optimization process.

4. Once the packaging process is finalised, the latest generation of MEMS chips will then be packaged, and management will use these chips with the intention of being able to demonstrate the technology to its full extent.

5. Despite using the older generations of packaged MEMS chips the yield was sufficient to assemble several evaluation boards proving the chips, algorithms, software and electronics are working as expected.

6. The company is in advanced stages of development of a stand-alone evaluation board that is capable of driving between 1 and 80 chips. This platform would be used to demonstrate sound performance, control algorithms, directivity manipulation and other advanced features of the technology.

Achievement of this milestone required overcoming rather extensive challenges to properly package the device in a manner that ensures that functional dies, while in wafer form, are not rendered inoperable as a result of the package or packaging process.

Packaging of a MEMS device is not only application specific, but has significant differences that render much of the equipment, tools and techniques commonly used to package conventional integrated circuits (IC’s), unusable. For example conventional pick-and-place tools, techniques and fixtures cannot be used to package a MEMS device, in order to avoid damaging the delicate surface features, the dies can only be handled from its sides, Another example is the inapplicability of many conventional adhesive materials and its application techniques when attaching the die or the lid to the substrate, as superfluous disbursement or unwarranted stress introduced by the adhesives, often leads to interference and failure of the devices micromechanical features. This among other reasons is why most chip packaging houses do not package MEMS, and those that do, inherently require a substantial “learning curve” and multiple development iterations.

Management is all the more gratified that it was able to achieve this critical milestone while being severely encumbered by the COVID-19 pandemic. Limitations and restrictions associated with the pandemic prohibited the hands-on interaction, inspection and guidance typically required for such activities. Not only did these circumstances extend timelines but it also necessitated extra iterations to achieve the desired objectives, which is why older generations of MEMS dies were preferred during development and stabilization of the packaging process. Nonetheless despite all these limitations the demonstration systems work as intended, and will continually improve in the coming weeks as the packaging process is optimized and we begin to introduce newer generations of MEMS dies into the chip packaging process.

This announcement has been authorised for release to ASX by Fred Bart, Chairman.

Some of you either seem to be ignorant of what has been announced or at least unfamiliar with the actual details. IMHO that gives no grounds for some of these unjustifiable doubts. DYOR.