CMOS Engineering Lead
Posted 19h agoAdd expected salary to your profile for insightsAbout the Company
Silicon Quantum Computing (SQC) is a leader in the global quantum computing industry. Our mission is to build the world’s first precision, high-quality, full-scale quantum computer unlocking transformative solutions to real-world challenges.
Quantum computing promises to revolutionise how information is processed and understood. It will enable the creation of faster, more efficient computers that will transform into the world’s most powerful artificial intelligence machines. SQC’s vision is to harness this groundbreaking technology, to improve human life and drive transformative change worldwide.
About the Role
Join one of Australia’s leading research teams at the forefront of atomic electronics and quantum computing.
We are seeking a highly experienced CMOS/ASIC mixed-signal design engineer with deep expertise in analogue design, to lead the development of custom integrated circuits for our quantum hardware platforms. This is a senior technical role encompassing the full ASIC development lifecycle—from architecture and specification through to layout and tapeout.
You will play a key role in designing and delivering high-performance mixed-signal ASICs, working closely with a multidisciplinary team of hardware and measurement engineers. Success in this role requires advanced analogue and mixed-signal design skills, hands-on experience with industry-standard EDA tools (such as Cadence, Synopsys, and/or Siemens), and a strong track record of delivering tapeout-ready silicon in commercial or research-driven applications.
The CMOS/ASIC Engineering Lead reports directly to the Chief Executive Officer and collaborates across engineering teams to drive innovation in silicon-based quantum computing.
Key Responsibilities
Lead or contribute to the analogue design of mixed-signal integrated circuits including blocks such as ADCs, DACs, LNAs, PLLs, filters, and other precision analogue components
Participate in system architecture definition and feasibility analysis
Execute the entire ASIC design flow, from schematic capture and simulation to layout, verification, sign-off, and tapeout
Perform detailed design reviews, verification, and post-layout simulations
Work collaboratively with foundries and EDA vendors to resolve process-related or tool-related issues
Maintain up-to-date knowledge of process technologies, best practices, and emerging tools
Cooperate with all health & safety policies and procedures of SQC.
Essential Experience
10+ years of experience in analogue and mixed-signal CMOS/ASIC design
Demonstrated tapeout experience with full life-cycle involvement (spec to silicon)
Expertise in analogue design fundamentals, including noise analysis, stability, matching, and layout-dependent effects
Fluency with EDA tools: One or more: Cadence Virtuoso, Synopsys Custom Designer, and/or Siemens EDA platforms
Familiarity with analogue layout and ability to work closely with layout engineers to guide floor planning and optimisation
Experience with scripting for automation is a plus
Strong communication, documentation, and cross-functional collaboration skills
Knowledge of health & safety responsibilities and commitment to attending relevant health and safety training.
Desirable Experience
Experience with FinFET, FDSOI, or BiCMOS processes
Knowledge of RF, high-speed interfaces, or sensor interface circuits
Prior experience in working with custom PDKs or developing IP blocks for reuse
Experience with lab evaluation and characterisation of silicon is a strong plus.
Company Culture
We foster a collaborative, diverse and inclusive environment where innovation and continuous learning are encouraged. Join us in our mission to pioneer cutting-edge technology to drive transformative changes across diverse industries.
Why Join Us?
At SQC, we are pioneering the future of quantum computing, with a focus on solving some of the world’s most complex problems. Join a team of world-class researchers, engineers, and innovators driving breakthroughs in science and technology.
Pre-Employment Checks Required
· Verification of qualifications
· Background checks
We look forward to receiving your applications. Please include a cover letter addressing the selection criteria.
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