still here mate
the issues that need addressing are not mentioned in the announcements
believe the underlying rto chamber / heat cycle oxidisation is the stumbling block
Samsung hit the same wall when they were playing with pcmo for a resistive memory
4DS hqve not dug as deep as manufacturing thermal stability off the back of the TEM / root cause...don't think they are even looking there'
but thats what a root cause is for to deconstruct the whole thing and re manufacture ....maybe they are not in a position to go thet deep
Samsungs' nvm rram pcmo experience - 2006 - 2008
they dropped it as it was considered an insurmountable issue to scale and maintain the 'stability'
However, it is difficult to form a PCMO film having a uniform perovskite structure, and a high-temperature process of 400 ° C. or more cannot be performed as a subsequent process due to problems such as deterioration of the variable resistor in the manufacturing process. In addition, in switching the resistance, a pulse of 1 ㎲ to 100 ㎲ and a voltage of 0.5 volt to 10 volt are required to decrease the resistance, and a pulse of 10 ㎱ to 1000 ㎱ and a voltage 1.5 to 2.5 times the voltage are required to increase the resistance. known to be necessary.
Seagate as well '56
seagate had it operational at 40nm and couldn't optimise performance or scale ....same stability issues
Micron ....same same as we know
Sharp as well 56 ...they mucked around with the etch mask incessantly and couldn't get through ....the issue is deeper imo
you can look all this up on the web - its freely available
so the big boys have had a crack and not found away through the stability wall to achieve scale
till these guys address this underlying fundamental and stop trying to fix the symptoms but dig into the problem it will go round in circles imo
to accuse IMEC of being part of the problem ( as some have) is unfair.....they simply bae the cake as we know
part of the new material research agreements involve the 'foundry' simply manufacture to customer spec - its then the customer remit to dig in and run qually and reveal the metrics ...which is exactly the play book that has been occurring here ...proof in the pudding and all that
best chance - functional 40nm pcmo chip ....believe they may have had a crack at 20/22nm and are finding these deeper issues at that geometry as per above
but '56 ....none of us know because we aren't privy to the inside run
I did not get caught here holding in the red - I trades out after the last lift before the 2nd 'failed' announcement and i've traded in and out since like quite a few others which is the go to here atm imo ....till something solid happens
I wait and hope they can turn it around...a breakthrough in the manufacture issues is the key but is that on the radar atm?
do I think they can - yeah - Its IMEC ....will they ?...
If this development process across the history of pcmo is well known in industry what chance a buyer will pop up without these guys going deeper?
all the above is just where I'm at with it mate - plenty of different views and opinions here hope they pull it out of the fire
all the best - Com
