| Analyst/Ann | Date |
| Bitmap | Retention |
| TMT Analytics | 10/09/2016 | x | 4DS announced it has achieved an endurance milestone for its Interface Switching (IS) ReRAM technology, i.e. 97% of the more than 1,000 memory cells the company has tested, achieved the minimum required number of switching cycles of 400 in a linear endurance test. A linear endurance test means that each cell is tested after every switch (a state change of the resistance level). So in total, all tested cells were switched more than 800 times at switching voltage of 20nA (set) and 10nA (reset).
In addition to achievement of the endurance milestone, the company has also demonstrated that it can drive endurance of individual cells well beyond this number of cycles through endurance optimization. Certain cells have achieved “well in excess” of 10,000 cycles (20,000 state changes per cell), which indicates that the cells should potentially be suitable for storage class memory applications, such as data storage in data centers and mobile devices at GB scale.
In NAND Flash memory today, Single Level Cells (SLC) can be switched approximately 100,000 times before failure, even though Flash vendors often limit the number of cycles to just 1,000 to prevent data loss. Therefore, we believe that 4DS will be able to achieve similar if not better endurance levels with its IS ReRAM cells, given that Interface Switching is a more durable technology. The 10,000+ cycles put IS ReRAM well within the realm of commercial applicability. | x |
| Shaw and Partners Flashnote | 28/10/2016 | Competitive next generation data centre storage technology hasn’t yet been commercialised. Interface Switching ReRAM is an emerging, non-volatile memory technology, unique to 4DS, that can potentially be scaled down to even smaller sizes, essential for data centres and cloud storage. We believe that 4DS is the only nonfilamentary ReRAM company with a global partner. The long lead times to develop such technology (10+ years),suggests that it is unlikely that there will be a short term challenge to the 4DS technology, which has been in development over the past decade, as the next generation non-volatile memory solution forecast to take US$6- 7b share of the US$40b Flash memory market by 2020. | Competitive next generation data centre storage technology hasn’t yet been commercialised. Interface Switching ReRAM is an emerging, non-volatile memory technology, unique to 4DS, that can potentially be scaled down to even smaller sizes, essential for data centres and cloud storage. We believe that 4DS is the only nonfilamentary ReRAM company with a global partner. The long lead times to develop such technology (10+ years),suggests that it is unlikely that there will be a short term challenge to the 4DS technology, which has been in development over the past decade, as the next generation non-volatile memory solution forecast to take US$6- 7b share of the US$40b Flash memory market by 2020. | Competitive next generation data centre storage technology hasn’t yet been commercialised. Interface Switching ReRAM is an emerging, non-volatile memory technology, unique to 4DS, that can potentially be scaled down to even smaller sizes, essential for data centres and cloud storage. We believe that 4DS is the only nonfilamentary ReRAM company with a global partner. The long lead times to develop such technology (10+ years),suggests that it is unlikely that there will be a short term challenge to the 4DS technology, which has been in development over the past decade, as the next generation non-volatile memory solution forecast to take US$6- 7b share of the US$40b Flash memory market by 2020. |
| Shaw and Partners Flashnote | 14/06/2017 | 4DS’s ReRAM is starting to tick all the boxes. The combination of speed and no errors that 4DS has reported, once incorporated into a 4DS ReRAM chip, will deliver most of the characteristics required. In order of importance, they are: non-volatile (4DS’s ReRAM ticks this box ), is fast to read (4DS ), excellent endurance (4DS ), high density (4DS ), reduced power consumption (4DS ), all while remaining affordable (4DS ). The last remaining box for 4DS to tick is data retention. A data retention update is expected next quarter; a retention closer to NAND FLASH than DRAM with read speed close to DRAM would be industry transforming. | 4DS’s ReRAM is starting to tick all the boxes. The combination of speed and no errors that 4DS has reported, once incorporated into a 4DS ReRAM chip, will deliver most of the characteristics required. In order of importance, they are: non-volatile (4DS’s ReRAM ticks this box ), is fast to read (4DS ), excellent endurance (4DS ), high density (4DS ), reduced power consumption (4DS ), all while remaining affordable (4DS ). The last remaining box for 4DS to tick is data retention. A data retention update is expected next quarter; a retention closer to NAND FLASH than DRAM with read speed close to DRAM would be industry transforming. | 4DS’s ReRAM is starting to tick all the boxes. The combination of speed and no errors that 4DS has reported, once incorporated into a 4DS ReRAM chip, will deliver most of the characteristics required. In order of importance, they are: non-volatile (4DS’s ReRAM ticks this box ), is fast to read (4DS ), excellent endurance (4DS ), high density (4DS ), reduced power consumption (4DS ), all while remaining affordable (4DS ). The last remaining box for 4DS to tick is data retention. A data retention update is expected next quarter; a retention closer to NAND FLASH than DRAM with read speed close to DRAM would be industry transforming. |
| Shaw and Partners Flashnote | 14/06/2017 | The competition has disappointed. Industry has invested billions looking for something to sit in between FLASH and DRAM, but 4DS is not aware of any other ReRAM technology that can make the same latency (read speed) claim that it now can and the only competing soon to be commercially available technology is 3D X Point by Intel and Micron. Initially they stated 3D XPoint would be 1000xs faster than NAND FLASH, it has since turned out to be a disappointing 10x faster leaving it miles behind DRAM (and now 4DS). It is 125x more dense than DRAM, but not that dense compared with NAND FLASH and it is expected to cost ~$2.40 per gigabyte (DRAM costs ~$5 per gig; FLASH is ~25 cents per gig). Despite all this disappointment industry observers still expect 3D XPoint will find a place in the market because the properties of DRAM and NAND FLASH are so far apart, there is room for many successful new memory products with very different properties. | The competition has disappointed. Industry has invested billions looking for something to sit in between FLASH and DRAM, but 4DS is not aware of any other ReRAM technology that can make the same latency (read speed) claim that it now can and the only competing soon to be commercially available technology is 3D X Point by Intel and Micron. Initially they stated 3D XPoint would be 1000xs faster than NAND FLASH, it has since turned out to be a disappointing 10x faster leaving it miles behind DRAM (and now 4DS). It is 125x more dense than DRAM, but not that dense compared with NAND FLASH and it is expected to cost ~$2.40 per gigabyte (DRAM costs ~$5 per gig; FLASH is ~25 cents per gig). Despite all this disappointment industry observers still expect 3D XPoint will find a place in the market because the properties of DRAM and NAND FLASH are so far apart, there is room for many successful new memory products with very different properties. | The competition has disappointed. Industry has invested billions looking for something to sit in between FLASH and DRAM, but 4DS is not aware of any other ReRAM technology that can make the same latency (read speed) claim that it now can and the only competing soon to be commercially available technology is 3D X Point by Intel and Micron. Initially they stated 3D XPoint would be 1000xs faster than NAND FLASH, it has since turned out to be a disappointing 10x faster leaving it miles behind DRAM (and now 4DS). It is 125x more dense than DRAM, but not that dense compared with NAND FLASH and it is expected to cost ~$2.40 per gigabyte (DRAM costs ~$5 per gig; FLASH is ~25 cents per gig). Despite all this disappointment industry observers still expect 3D XPoint will find a place in the market because the properties of DRAM and NAND FLASH are so far apart, there is room for many successful new memory products with very different properties. |
| Mac Equity Partners | 13th June 2017 | x | 4DS has announced it’s closer to proving the commercial viability of its Storage Class Memory technology, as they have achieved size and yield milestones desirable to memory manufacturers. Since 2014, 4DS has consistently decreased the size of its working cells from 800nm to 40nm. 40nm is a breakthrough as it is below the current size of conventional 3D Flash memory of between 45nm to 50nm. The ability to scale down to this size is fundamental to creating stacked IS ReRAM into 3D structures essential for Storage Class Memory.
In late 2016 4DS achieved an endurance yield of 97% as measured by an independent technical expert signifying how often the state of a memory cell can be changed without failure. (3)
This high endurance rate is essential for supporting high capacity data storage applications. (4)
4DS will continue to follow its development timeline to ensure essential milestones are accomplished in 2017. | x |
| Mac Equity Partners | 13th June 2017 | 4DS today announced to ASX that it has achieved a world first by reaching the same speed as DRAM.
This milestone has been unattainable for most emerging memory technologies due to large random cell current fluctuation.
This in turn requires complex error-correction techniques which affect read access time and cripples read speed. | x | x |
| TMT Analytics | 31 August 2017 | The hoops that every new memory technology needs to jump through
In order to validate a particular storage technology, all memory developers follow a very specific development process. During this multi-year process, memory cells are scaled down towards a certain target resolution and then characterized for cycling endurance, access speed and data retention. The cell architecture and manufacturing process is then further optimized to achieve the targeted goals for these metrics. Memory device performance is measured on the following key metrics: Access speed: The speed at which data can be written and read is called access speed. This needs to be sufficiently fast to make the technology suitable for various applications. Through its development work 4DS has recently achieved read speeds for Interface Switching ReRAM that are comparable to DRAM read speeds of approximately 50 nanoseconds. By comparison, Flash memory can achieve read speeds of around 50,000 nanoseconds. In other words, Flash memory is around 1,000 times slower than Interface Switching ReRAM.
Furthermore, Interface Switching ReRAM can be read with near-zero errors, therefore requiring very limited error correction. Certain other emerging storage technologies that can achieve high read speeds require substantial error corrections, which to a considerable extent cancel out the achieved speed gains.
DRAM-like read speeds with near-zero error correction is a ground-breaking achievement for a non-volatile memory technology and will likely have sparked serious industry interest | Cycling endurance: The number of times a memory cell can be switched from a low resistive state (LRS representing a value of 1) to a high resistive state (HRS representing a value of 0) and back without failure is called cycling endurance. Today’s multi level cell (MLC) Flash memory has a relatively limited number of so-called program-erase cycles (PE cycles), typically between 1,000 and 10,000 cycles, i.e. a relatively low cycling endurance. Single level cells can achieve up to 100,000 PE cycles. 4DS has indicated that Interface Switching ReRAM has achieved cycling endurance for a number of its memory cells well in excess of 100,000. We expect that the technology can be further developed in the next few years to achieve an even longer cycling endurance for end applications that may have such requirements | Data retention reflects the amount of time a memory cell can stay in a LRS or HRS, and thus represent a value of 1 or 0. Data retention will typically improve with higher electrical currents being used to switch memory cells. However, higher currents may result in memory cells degrading faster. So, a balance between the two needs to be found, again depending on the specific end application.
Furthermore, data retention depends on cell temperature and the number of PE cycles a cell has gone through, i.e. data retention of a specific memory cell will improve at lower temperatures, but will deteriorate with an increasing number of PE cycles.
The higher currents used to achieve DRAM speed should have positive effect on retention
In June 2017, 4DS indicated it had increased the electrical currents used to switch its memory cells in order to achieve DRAM-like access speeds (higher currents lead to better data write results and hence fewer read-out problems).
Higher switching currents typically also result in better data retention. In other words, even though 4DS indicated in June that it will need to make further technological progress on data retention, we believe the higher switching currents the company is now applying in IS ReRAM will lead to better data retention compared to late 2016, when the company already mentioned encouraging data retention results.
While 4DS will obviously still need to confirm and announce data retention results that will be satisfactory for prospective acquirers of the technology, we are quite confident the company will be able to achieve this in the near term, especially given the development team’s solid track record of delivering on technical milestones. |
| Mac Equity Partners | 27/11/2017 | Nov 2017
4DS Interface Switching ReRAM has displayed enough relevant and meaningful data in each category to now move immediately to production of a Megabit chip, a giant step forward.
1. Scales to geometries needed for high-density memory and 3D : 40nm memory cell
2. Endurance far exceeds NAND Flash
3. Current retention data adequate for Storage Class Memory
4. Endurance yield >97%
5. Read speed comparable to DRAM – an area-based ReRAM first
6. No need for speed crippling error correction – a ReRAM first | Nov 2017
4DS Interface Switching ReRAM has displayed enough relevant and meaningful data in each category to now move immediately to production of a Megabit chip, a giant step forward.
1. Scales to geometries needed for high-density memory and 3D : 40nm memory cell
2. Endurance far exceeds NAND Flash
3. Current retention data adequate for Storage Class Memory
4. Endurance yield >97%
5. Read speed comparable to DRAM – an area-based ReRAM first
6. No need for speed crippling error correction – a ReRAM first | Nov 2017
4DS Interface Switching ReRAM has displayed enough relevant and meaningful data in each category to now move immediately to production of a Megabit chip, a giant step forward.
1. Scales to geometries needed for high-density memory and 3D : 40nm memory cell
2. Endurance far exceeds NAND Flash
3. Current retention data adequate for Storage Class Memory
4. Endurance yield >97%
5. Read speed comparable to DRAM – an area-based ReRAM first
6. No need for speed crippling error correction – a ReRAM first |
| Mac Equity Partners | 26/11/2017 | x | x | 25 Nov 2017
The Last Milestone - Data Retention As previously noted in our research and the Company’s regular ASX announcements, 4DS was developing their technology through the achievement of four critical milestones, being scalability, endurance, access speed and data retention. Given the collaboration agreement with imec and the extensive due diligence that would have taken place, we have concluded that the data retention results to date have given imec confidence to progress with a collaboration and we consider that last milestone all but complete. This was reinforced by 4DS’ presentation lodged with ASX on 24 November 2017. |
| Mac Equity Partners | 27/11/2017 | Prospective customers to base license or buy decision on data from final chip Once the integration is completed, 4DS will collect statistically significant and meaningful data on yield, endurance, speed and data retention, essential for high-volume memory manufacturers (such as SK Hynix, Samsung, Intel, SanDisk (owned by Western Digital) and Micron) in their decision-making process around licensing or potentially acquiring 4DS’ technology, which we believe may happen in 2020. | Prospective customers to base license or buy decision on data from final chip Once the integration is completed, 4DS will collect statistically significant and meaningful data on yield, endurance, speed and data retention, essential for high-volume memory manufacturers (such as SK Hynix, Samsung, Intel, SanDisk (owned by Western Digital) and Micron) in their decision-making process around licensing or potentially acquiring 4DS’ technology, which we believe may happen in 2020. | Prospective customers to base license or buy decision on data from final chip Once the integration is completed, 4DS will collect statistically significant and meaningful data on yield, endurance, speed and data retention, essential for high-volume memory manufacturers (such as SK Hynix, Samsung, Intel, SanDisk (owned by Western Digital) and Micron) in their decision-making process around licensing or potentially acquiring 4DS’ technology, which we believe may happen in 2020. |
| Company Ann | 24/06/2020 | 24-June-20
Additional Wafers Lot
As of today’s date, the Company is pleased to confirm that it has measured the highest speed and endurance in the Additional Wafers Lot that have ever been recorded by the Company:
− The best recorded speed at near DRAM speed exceeds Storage Class Memory requirements without the need for speed crippling error correction;
− Endurance is two to three times better than previously reported. Actual endurance may be significantly higher but is currently not quantified due to available lab time and test equipment capacity; and
−The Company also measured retention and the results remain confidential to the Company and its partners until such time the upper limits of retention can be more accurately defined.
Initial Platform Lot
− Testing of the Initial Platform Lot validated the integration process stepsrequired to integrate 4DS memory cells with imec’s megabit platform. The information gathered from this testing has enabled 4DS to identify which process steps will be further tuned, to benefit future platform iterations. | 24-June-20
Additional Wafers Lot
As of today’s date, the Company is pleased to confirm that it has measured the highest speed and endurance in the Additional Wafers Lot that have ever been recorded by the Company:
− The best recorded speed at near DRAM speed exceeds Storage Class Memory requirements without the need for speed crippling error correction;
− Endurance is two to three times better than previously reported. Actual endurance may be significantly higher but is currently not quantified due to available lab time and test equipment capacity; and
−The Company also measured retention and the results remain confidential to the Company and its partners until such time the upper limits of retention can be more accurately defined.
Initial Platform Lot
− Testing of the Initial Platform Lot validated the integration process stepsrequired to integrate 4DS memory cells with imec’s megabit platform. The information gathered from this testing has enabled 4DS to identify which process steps will be further tuned, to benefit future platform iterations. | 24-June-20
Additional Wafers Lot
As of today’s date, the Company is pleased to confirm that it has measured the highest speed and endurance in the Additional Wafers Lot that have ever been recorded by the Company:
− The best recorded speed at near DRAM speed exceeds Storage Class Memory requirements without the need for speed crippling error correction;
− Endurance is two to three times better than previously reported. Actual endurance may be significantly higher but is currently not quantified due to available lab time and test equipment capacity; and
−The Company also measured retention and the results remain confidential to the Company and its partners until such time the upper limits of retention can be more accurately defined.
Initial Platform Lot
− Testing of the Initial Platform Lot validated the integration process stepsrequired to integrate 4DS memory cells with imec’s megabit platform. The information gathered from this testing has enabled 4DS to identify which process steps will be further tuned, to benefit future platform iterations. |
| Pitt St Research mark Kennis | 23/09/2020 | Major milestone achieved during lockdown In June 2020, 4DS shared a key update on the status of the development of its Interface Switching ReRAM technology. It announced that it had made significant technical progress with regard to the analysis of the wafers it received from its collaboration partner imec, coupled with technical inputs from HGST – Western Digital’s wholly owned subsidiary.
The company highlighted that it had measured the highest speed and endurance ever recorded in the Additional Wafers Lot. Notably, it achieved the best recorded speed at near DRAM speed, exceeding storage class memory (SCM) requirements, coupled with endurance levels, which were two to three times better than previously reported.
Further, it also completed analysis on its Initial Platform Lot of 300mm wafers, which combine 4DS’ memory cell arrays with imec's megabit platform. The integration of the two technologies is a very important step in development of the end product. Testing revealed 4DS also achieved read/write speeds comparable to DRAM, which will be beneficial for SCM applications.
The company also tested data retention in its memory cells, another key performance metric, but indicated additional studies need to be completed in order to assess the upper limits.
The analyses have helped the company identify process steps that need to be refined further to benefit future platform iterations. Based on the wafer testing results and identification of further iterative improvement steps, we believe that 4DS has moved a step closer towards its goal of delivering a megabit chip | Major milestone achieved during lockdown In June 2020, 4DS shared a key update on the status of the development of its Interface Switching ReRAM technology. It announced that it had made significant technical progress with regard to the analysis of the wafers it received from its collaboration partner imec, coupled with technical inputs from HGST – Western Digital’s wholly owned subsidiary.
The company highlighted that it had measured the highest speed and endurance ever recorded in the Additional Wafers Lot. Notably, it achieved the best recorded speed at near DRAM speed, exceeding storage class memory (SCM) requirements, coupled with endurance levels, which were two to three times better than previously reported.
Further, it also completed analysis on its Initial Platform Lot of 300mm wafers, which combine 4DS’ memory cell arrays with imec's megabit platform. The integration of the two technologies is a very important step in development of the end product. Testing revealed 4DS also achieved read/write speeds comparable to DRAM, which will be beneficial for SCM applications.
The company also tested data retention in its memory cells, another key performance metric, but indicated additional studies need to be completed in order to assess the upper limits.
The analyses have helped the company identify process steps that need to be refined further to benefit future platform iterations. Based on the wafer testing results and identification of further iterative improvement steps, we believe that 4DS has moved a step closer towards its goal of delivering a megabit chip | Major milestone achieved during lockdown In June 2020, 4DS shared a key update on the status of the development of its Interface Switching ReRAM technology. It announced that it had made significant technical progress with regard to the analysis of the wafers it received from its collaboration partner imec, coupled with technical inputs from HGST – Western Digital’s wholly owned subsidiary.
The company highlighted that it had measured the highest speed and endurance ever recorded in the Additional Wafers Lot. Notably, it achieved the best recorded speed at near DRAM speed, exceeding storage class memory (SCM) requirements, coupled with endurance levels, which were two to three times better than previously reported.
Further, it also completed analysis on its Initial Platform Lot of 300mm wafers, which combine 4DS’ memory cell arrays with imec's megabit platform. The integration of the two technologies is a very important step in development of the end product. Testing revealed 4DS also achieved read/write speeds comparable to DRAM, which will be beneficial for SCM applications.
The company also tested data retention in its memory cells, another key performance metric, but indicated additional studies need to be completed in order to assess the upper limits.
The analyses have helped the company identify process steps that need to be refined further to benefit future platform iterations. Based on the wafer testing results and identification of further iterative improvement steps, we believe that 4DS has moved a step closer towards its goal of delivering a megabit chip |
| Pitt St Research mark Kennis | 24/09/2020 | More importantly, WDC regards ReRAM as better scalable than 3D XPoint, a technology engineered by Intel and Micron, which is saying quite a lot given that 3D XPoint technology is considered to having substantial benefits in the areas of speed, endurance and scalability, albeit at a premium price. So WDC stating that it considers ReRAM to be better scalable than 3D XPoint, is extremely bullish for 4DS, in our view. TMT analytics 10/9/2016
Total revenues for 3D XPoint are expected to reach US$3BN by 2023 and US$16BN by 2029. In other words, Interface Switching ReRAM, which is technologically superior to 3D XPoint mainly due to better read/write speeds, would present a very substantial revenue opportunity in the right hands, i.e. existing players or challengers in the SCM space. | More importantly, WDC regards ReRAM as better scalable than 3D XPoint, a technology engineered by Intel and Micron, which is saying quite a lot given that 3D XPoint technology is considered to having substantial benefits in the areas of speed, endurance and scalability, albeit at a premium price. So WDC stating that it considers ReRAM to be better scalable than 3D XPoint, is extremely bullish for 4DS, in our view. TMT analytics 10/9/2016
Total revenues for 3D XPoint are expected to reach US$3BN by 2023 and US$16BN by 2029. In other words, Interface Switching ReRAM, which is technologically superior to 3D XPoint mainly due to better read/write speeds, would present a very substantial revenue opportunity in the right hands, i.e. existing players or challengers in the SCM space. | More importantly, WDC regards ReRAM as better scalable than 3D XPoint, a technology engineered by Intel and Micron, which is saying quite a lot given that 3D XPoint technology is considered to having substantial benefits in the areas of speed, endurance and scalability, albeit at a premium price. So WDC stating that it considers ReRAM to be better scalable than 3D XPoint, is extremely bullish for 4DS, in our view. TMT analytics 10/9/2016
Total revenues for 3D XPoint are expected to reach US$3BN by 2023 and US$16BN by 2029. In other words, Interface Switching ReRAM, which is technologically superior to 3D XPoint mainly due to better read/write speeds, would present a very substantial revenue opportunity in the right hands, i.e. existing players or challengers in the SCM space. |
| Company Ann | 25/11/2020 | 25-Nov-20
In 2020, 4DS Interface Switching ReRAM showed record
achievements in relevant Storage Class Memory categories:
Best endurancedata recorded – two to three times better than previously reported* asx 24/6/20
Highest recorded speed near DRAM speed– an area based ReRAM first– US patents now granted* asx 24/6
No need for speed crippling error correction–a ReRAM first– US patents now granted
Retention data recorded– additional studies to be completed to assess upper limits
Data validated by two of the world’s leading semiconductor participants– imec / HGST | 25-Nov-20
In 2020, 4DS Interface Switching ReRAM showed record
achievements in relevant Storage Class Memory categories:
Best endurancedata recorded – two to three times better than previously reported* asx 24/6/20
Highest recorded speed near DRAM speed– an area based ReRAM first– US patents now granted* asx 24/6
No need for speed crippling error correction–a ReRAM first– US patents now granted
Retention data recorded– additional studies to be completed to assess upper limits
Data validated by two of the world’s leading semiconductor participants– imec / HGST | 25-Nov-20
In 2020, 4DS Interface Switching ReRAM showed record
achievements in relevant Storage Class Memory categories:
Best endurancedata recorded – two to three times better than previously reported* asx 24/6/20
Highest recorded speed near DRAM speed– an area based ReRAM first– US patents now granted* asx 24/6
No need for speed crippling error correction–a ReRAM first– US patents now granted
Retention data recorded– additional studies to be completed to assess upper limits
Data validated by two of the world’s leading semiconductor participants– imec / HGST |
| Company Ann | 1/02/2021 | Further to the update provided in the Company’s Quarterly Activity Report dated 20 January 2021, 4DS confirms that it has now completed its testing of the Second Non-Platform Lot. The Company is pleased to report that the data from the Second Non-Platform Lot: − Confirmed that the Company has been able to repeat the results for each of the key memory characteristics (speed, endurance and retention) that were achieved with the First Non-Platform Lot;
− significantly, 19 of the 21 device wafers were functional, a first for the Company (the two nonfunctional wafers were the result of being manufactured outside the imec process window); and
− provides 4DS with further valuable insights with respect to how changes in key process parameters affect these key memory characteristics; i.e. which changes increase which memory characteristic. | Further to the update provided in the Company’s Quarterly Activity Report dated 20 January 2021, 4DS confirms that it has now completed its testing of the Second Non-Platform Lot. The Company is pleased to report that the data from the Second Non-Platform Lot: − Confirmed that the Company has been able to repeat the results for each of the key memory characteristics (speed, endurance and retention) that were achieved with the First Non-Platform Lot;
− significantly, 19 of the 21 device wafers were functional, a first for the Company (the two nonfunctional wafers were the result of being manufactured outside the imec process window); and
− provides 4DS with further valuable insights with respect to how changes in key process parameters affect these key memory characteristics; i.e. which changes increase which memory characteristic. | Further to the update provided in the Company’s Quarterly Activity Report dated 20 January 2021, 4DS confirms that it has now completed its testing of the Second Non-Platform Lot. The Company is pleased to report that the data from the Second Non-Platform Lot: − Confirmed that the Company has been able to repeat the results for each of the key memory characteristics (speed, endurance and retention) that were achieved with the First Non-Platform Lot;
− significantly, 19 of the 21 device wafers were functional, a first for the Company (the two nonfunctional wafers were the result of being manufactured outside the imec process window); and
− provides 4DS with further valuable insights with respect to how changes in key process parameters affect these key memory characteristics; i.e. which changes increase which memory characteristic. |
