Cheers Guv, there's some meat sure left on them bones for picking...
Now lest see what "the Dige" got cooking.... Course they all over re-ram products they been heavy in to early iterations for years and have pinned their future on new re-ram tech to market.. And lets remember it was WDC who specifically asked for the add lot to be constructed using the "special juice Process conditions profile" and they predict an uplift on SCM occurring from 2020 onwards.. Whilst possibly predicting the demise of Optane early on..... Enter the new contender. And if anyone can cost scale a new SCM product straight off the bat it's WDC & Co
If you think this looks familiar you are probably right.. 4DS has a new tech product that will occupy a matrix space in the low left hand corner, the cost of Flash and the Speed of or near DRAM
Speed in one qtr and then retention/endurance in another
We have all seen the slides yada yada yada and the metrics of it....
So why aren't they sticking with what works already.. Well because DRAM can't scale & Flash can't last a lifetime.
With the anticipated scaling issues of DRAM memory technology and the increased need for higher density and bandwidth, several alternative memory technologies are being explored for the main memory system. One promising candidate is a variation of Resistive Random-Access Memory (ReRAM) which implements the memory bit-cells on Back-End-of-Line (BEOL) layers. This allows for fabrication of the processor logic and ReRAM main-memory to be implemented on the same chip. As the memory cells can be stacked vertically, the density of this memory also scales to 1-4F2. This tight integration allows for a high amount of parallelism between the processor and memory systems and delivers low access granularity without sacrificing density or bandwidth. Our results indicate that, in addition to the overhead for the ReRAM access circuits, the overall integrated area increases by 11% to 19%, based on the configuration at the 45nm process node. Results from architectural simulation comparing DRAM with ReRAM based architecture are presented.
Emerging Resistive Memory (ReRAM) is a promising candidate as the replacement for DRAM because of its low power consumption, high density and high endurance.
With semiconductor manufacturers continuously working to make computer memory chips smaller and smaller, Flash memory has started to run into the limits set by physics. Flash memory is the work horse of data storage, but Flash memory cells just can't get any smaller without malfunctioning. And that is a big problem in a world where video content is being created at an exponentially growing rate due to the popularity of YouTube, Netflix and social media. With every new phone, we want more storage capacity, which is why new technologies are being developed. 4DS Memory (ASX:4DS) is working on one of the front runners in the Next Gen memory space and the technology the company is working on received public endorsement from storage giant Western Digital. Time for a closer look.This so-called cell-to-cell interference is particularly problematic for certain types of memory chips that use an electrical charge to store information, such as Flash memory, which is used in a whole range of electronic products, such as iPhones, tablets, laptops, smart watches and cars. When the electrical charge in a Flash memory cell starts to leak away, the value stored in that memory cell can become corrupted. If this happens to a sufficiently large number of memory cells in a chip, you can kiss your stored data goodbye.
Recently, multiple non-volatile emerging memories (NVMs) have been proposed and show promising properties to replace SRAM-based memories in future SoCs. We show that for single benchmarks the performance penalty caused by the ReRAM write latency can be reduced to 7% for the complete wireless communication benchmark suite.
"which is used in a whole range of electronic products, such as iPhones, tablets, laptops, smart watches and cars". so the 4DS product could also effectively replace both the SRAM & Flash modules in this type of "System on Chip" application... Enter Nvidia
The patent was lodged and based on that fact under the classification BACKGROUND OF THE INVENTION Storage Class Memory is an emerging non-volatile memory segment positioned between the most successful system memory (DRAM) and the most successful silicon storage (NAND Flash). There are many opportunities for new memories in the vast space between DRAM and NAND Flash, each with different speed, endurance and retention metrics.
The ultimate market demand is therefore for Storage Class Memory with DRAM speed, the highest endurance achievable with this speed, a cost per gigabyte closer to NAND Flash, and a pragmatic retention far superior to DRAM retention.
Furthermore, certain semiconductor memory technologies have applied a principal of geometric redundancy, where multiple data bits may be stored in a single cell. This property of a memory cell to support a multiple of values is sometimes referred to as its dynamic range.
To date the for memory cells have abilities to support a dynamic range anywhere between 1 and 4 bits. These combined properties of semiconductors have increased capacities and reduced costs.
DETAILED DESCRIPTION OF THE INVENTION The present invention is related to a nonvolatile memory device. The memory device can be utilized in a variety of applications from a free standing nonvolatile memory to an embedded device in a variety of applications. These applications include but are not limited to embedded memory used in a wide range of SOC (system on chip), switches in programmable or configurable ASIC, solid state drive used in computers and servers, memory sticks used in mobile electronics like camera, cell phone, iPod® etc.
Particular embodiments of the invention are illustrated herein in conjunction with the drawings and noting that the patent applies to an array of devices with the patented difference providing the following cost benefit.
The cost of memories using an array of memory devices as described herein is much less than that of memories which use traditional non-volatile memory cells, such as DRAM cells.
This is the case at least because of the following differences resulting from one or more of the features discussed herein as understood by those of skill in the art: 1) Memory devices discussed herein have area that is much smaller than DRAM cells, 2) The manufacturing process for making DRAM cells typically includes forming a trench in the substrate, for example, for forming a capacitor, while memory devices such as memory device 100 may be manufactured without forming a trench.
The particular patent relates to;
Memory devices shown 200 - 800 being the same in that;
In memory device 800, top barrier layer 820 has little or a substantially zero oxygen ion diffusion coefficient, such that the oxygen ions and vacancies are confined to top electrode layer 830, retention layer 840 (if present), and memory layer 850 by top barrier layer 820. As a result, the reliability of memory device 800 is excellent.
So whilst the retention and endurance reliability are reported as excellent the real kicker is the speed of operation & that is the field where the patent sits... 4DS ability to control variable resistance on a non filamentary interface switch arrangement is totally unique and offers not only excellent reliability & retention across all applications and sizes uniformly, but it does it at near DRAM speed without error.
DETAILED DESCRIPTION OF THE INVENTION The speed or access time of memories using an array of memory devices as described herein is much better than that of memories which use traditional non-volatile memory cells. This is the case at least because the electrical resistance of the layers and contacts outside of the memory layer is low, as discussed above with reference to each of the layers and contacts. Memory speed using memory devices as described herein is also improved over traditional memories because large memory systems using memory devices as described herein may be operated without speed crippling Error Correction Code (ECC) techniques as a result, for example, of reliable retention of the memory states of the memory devices. For example, memory systems having Megabyte, Gigabyte, Terabyte storage may be operated without speed crippling ECC techniques.
Western Digital already know the importance of the above and already anticipate moving terabytes of data at DRAM speed, yet at 1/5th of the cost.
SO yes it stands t reason that WDC have been heavily involved in this space... The company has pinned future growth on this segment and can hardly sit on their hands and wait for the next big thing..
However, if the next big thing were to arrive then there is no better way to gain market acceptance & share than to ramp up a new product in to existing lines as a cost benefit replacement on like for like basis..
WDC is already building like type devices using available tech and supplying the market presently, you would expect them to be doing so it's how they put food on the table..
What any new tech brings will be a cost comparative & possibly superior replacement which integrates seamlessly in to current product lines and potentially opens up more.
Now to me, that sounds like good business more so than a little espionage don't it?
You put the kettle on Doc, & I'll go warm up the pan.....
With the anticipated scaling issues of DRAM memory technology and the increased need for higher density and bandwidth, several alternative memory technologies are being explored for the main memory system. One promising candidate is a variation of Resistive Random-Access Memory (ReRAM) which implements the memory bit-cells on Back-End-of-Line (BEOL) layers. This allows for fabrication of the processor logic and ReRAM main-memory to be implemented on the same chip. As the memory cells can be stacked vertically, the density of this memory also scales to 1-4F2. This tight integration allows for a high amount of parallelism between the processor and memory systems and delivers low access granularity without sacrificing density or bandwidth. Our results indicate that, in addition to the overhead for the ReRAM access circuits, the overall integrated area increases by 11% to 19%, based on the configuration at the 45nm process node. Results from architectural simulation comparing DRAM with ReRAM based architecture are presented.
